package arm64 import ( "testing" "github.com/tetratelabs/wazero/internal/asm" "github.com/tetratelabs/wazero/internal/testing/require" ) func TestAssemblerImpl_EncodeRegisterToMemory(t *testing.T) { t.Run("error", func(t *testing.T) { tests := []struct { n *nodeImpl expErr string }{ { n: &nodeImpl{instruction: ADR, types: operandTypesRegisterToMemory}, expErr: "ADR is unsupported for RegisterToMemory type", }, } code := asm.CodeSegment{} defer func() { require.NoError(t, code.Unmap()) }() for _, tt := range tests { tc := tt a := NewAssembler(asm.NilRegister) buf := code.NextCodeSection() err := a.encodeRegisterToMemory(buf, tc.n) require.EqualError(t, err, tc.expErr) } }) tests := []struct { name string n *nodeImpl exp []byte }{ {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x40, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x8, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x28, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x8, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x10, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x0, 0xfc, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xf8}}, {name: "STRD/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x43, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0xb, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x2b, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x8, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x10, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xc0, 0xff, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xf8}}, {name: "STRD/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x40, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x8, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x28, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x8, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x10, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1e, 0xfc, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xf8}}, {name: "STRD/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x43, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0xb, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x2b, 0x0, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x8, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x10, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xde, 0xff, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xf9}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, {name: "STRD/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xf8}}, {name: "STRD/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRD, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xf8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x4, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x10, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x50, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x10, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x20, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xb8}}, {name: "STRW/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x7, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x13, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x53, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x10, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x20, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xb8}}, {name: "STRW/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x4, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x10, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x50, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x10, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x20, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xb8}}, {name: "STRW/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x7, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x13, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x53, 0x0, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x10, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x20, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xb9}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, {name: "STRW/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xb8}}, {name: "STRW/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRW, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xb8}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x4, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x8, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x20, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0xa0, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x20, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x60, 0x3, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x18, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x60, 0xd3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x78}}, {name: "STRH/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x7, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0xb, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x23, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0xa3, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x20, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x60, 0x3, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1b, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x60, 0xd3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x78}}, {name: "STRH/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x4, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x8, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x20, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0xa0, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x20, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x18, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x7e, 0xd3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x38, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x78}}, {name: "STRH/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x7, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0xb, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x23, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0xa3, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x20, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1b, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x7e, 0xd3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3b, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x79}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, {name: "STRH/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x78}}, {name: "STRH/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRH, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0x78}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x4, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x8, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x10, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0x3c, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x40, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0x3c, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x44, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x40, 0x1, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xfc, 0x3, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1b, 0x4, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x1c, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x60, 0xa3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x60, 0x83, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0x38}}, {name: "STRB/RegisterOffset/src=R0,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x7, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0xb, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x13, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0x3f, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x43, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0x3f, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x47, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x43, 0x1, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xff, 0x3, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xdb, 0x7, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x60, 0x3, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1f, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x60, 0xc3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x60, 0xa3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x60, 0x83, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0x38}}, {name: "STRB/RegisterOffset/src=R0,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x4, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x8, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x10, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0x3c, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x40, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0x3c, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x44, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x40, 0x1, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xfc, 0x3, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1b, 0x4, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1b, 0x8, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x1c, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x7e, 0xa3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x3c, 0x40, 0x91, 0x7e, 0x83, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0x38}}, {name: "STRB/RegisterOffset/src=R30,base=R0,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x7, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x2", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0xb, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x4", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x13, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0x3f, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x10", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x43, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xf", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0x3f, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x11", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x47, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x50", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x43, 0x1, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xff", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xff, 0x3, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x1000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xdb, 0x7, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x2000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xdb, 0xb, 0x40, 0x91, 0x7e, 0x3, 0x0, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x1f, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x7e, 0xc3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x7e, 0xa3, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x3f, 0x40, 0x91, 0x7e, 0x83, 0x3f, 0x39}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, {name: "STRB/ConstOffset/src=R30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0x38}}, {name: "STRB/RegisterOffset/src=R30,base=R30,offset=RegR8", n: &nodeImpl{instruction: STRB, srcReg: RegR30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0x38}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x40, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x8, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x28, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x8, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x10, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x0, 0xfc, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/RegisterOffset/src=V0,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x43, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0xb, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x2b, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x8, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x10, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xc0, 0xff, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf7, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/RegisterOffset/src=V0,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x40, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x8, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x28, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x8, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x10, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1e, 0xfc, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x20, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xfc}}, {name: "FSTRD/RegisterOffset/src=V30,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x43, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0xb, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x2b, 0x0, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x8, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x10, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xde, 0xff, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf7, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x23, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xfd}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/ConstOffset/src=V30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xfc}}, {name: "FSTRD/RegisterOffset/src=V30,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRD, srcReg: RegV30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xfc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -1}, exp: []byte{0x0, 0xf0, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 0}, exp: []byte{0x0, 0x0, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1}, exp: []byte{0x0, 0x10, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 2}, exp: []byte{0x0, 0x20, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -2}, exp: []byte{0x0, 0xe0, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 4}, exp: []byte{0x0, 0x4, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -4}, exp: []byte{0x0, 0xc0, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -15}, exp: []byte{0x0, 0x10, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 16}, exp: []byte{0x0, 0x10, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 15}, exp: []byte{0x0, 0xf0, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 17}, exp: []byte{0x0, 0x10, 0x1, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -256}, exp: []byte{0x0, 0x0, 0x10, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 80}, exp: []byte{0x0, 0x50, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: -128}, exp: []byte{0x0, 0x0, 0x18, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 255}, exp: []byte{0x0, 0xf0, 0xf, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x0, 0x0, 0x10, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x0, 0x0, 0x20, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x0, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/RegisterOffset/src=V0,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x0, 0x68, 0x28, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -1}, exp: []byte{0xc0, 0xf3, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 0}, exp: []byte{0xc0, 0x3, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1}, exp: []byte{0xc0, 0x13, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 2}, exp: []byte{0xc0, 0x23, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -2}, exp: []byte{0xc0, 0xe3, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 4}, exp: []byte{0xc0, 0x7, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -4}, exp: []byte{0xc0, 0xc3, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -15}, exp: []byte{0xc0, 0x13, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 16}, exp: []byte{0xc0, 0x13, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 15}, exp: []byte{0xc0, 0xf3, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 17}, exp: []byte{0xc0, 0x13, 0x1, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -256}, exp: []byte{0xc0, 0x3, 0x10, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 80}, exp: []byte{0xc0, 0x53, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: -128}, exp: []byte{0xc0, 0x3, 0x18, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 255}, exp: []byte{0xc0, 0xf3, 0xf, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xc0, 0x3, 0x10, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xc0, 0x3, 0x20, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x60, 0xfb, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xf3, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xeb, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x60, 0xe3, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V0,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xc0, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/RegisterOffset/src=V0,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV0, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xc0, 0x6b, 0x28, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -1}, exp: []byte{0x1e, 0xf0, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 0}, exp: []byte{0x1e, 0x0, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1}, exp: []byte{0x1e, 0x10, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 2}, exp: []byte{0x1e, 0x20, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -2}, exp: []byte{0x1e, 0xe0, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 4}, exp: []byte{0x1e, 0x4, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -4}, exp: []byte{0x1e, 0xc0, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -15}, exp: []byte{0x1e, 0x10, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 16}, exp: []byte{0x1e, 0x10, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 15}, exp: []byte{0x1e, 0xf0, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 17}, exp: []byte{0x1e, 0x10, 0x1, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -256}, exp: []byte{0x1e, 0x0, 0x10, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 80}, exp: []byte{0x1e, 0x50, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: -128}, exp: []byte{0x1e, 0x0, 0x18, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 255}, exp: []byte{0x1e, 0xf0, 0xf, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 4096}, exp: []byte{0x1e, 0x0, 0x10, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 8192}, exp: []byte{0x1e, 0x0, 0x20, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 32760}, exp: []byte{0x1b, 0x10, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 65520}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 65512}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 65504}, exp: []byte{0x1b, 0x30, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R0,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0x1e, 0x68, 0x3b, 0xbc}}, {name: "FSTRS/RegisterOffset/src=V30,base=R0,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR0, dstReg2: RegR8}, exp: []byte{0x1e, 0x68, 0x28, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffffff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -1}, exp: []byte{0xde, 0xf3, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 0}, exp: []byte{0xde, 0x3, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1}, exp: []byte{0xde, 0x13, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x2", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 2}, exp: []byte{0xde, 0x23, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffe", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -2}, exp: []byte{0xde, 0xe3, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x4", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 4}, exp: []byte{0xde, 0x7, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffffc", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -4}, exp: []byte{0xde, 0xc3, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfffffffffffffff1", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -15}, exp: []byte{0xde, 0x13, 0x1f, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x10", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 16}, exp: []byte{0xde, 0x13, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xf", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 15}, exp: []byte{0xde, 0xf3, 0x0, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x11", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 17}, exp: []byte{0xde, 0x13, 0x1, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff00", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -256}, exp: []byte{0xde, 0x3, 0x10, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x50", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 80}, exp: []byte{0xde, 0x53, 0x0, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffffffffffffff80", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: -128}, exp: []byte{0xde, 0x3, 0x18, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xff", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 255}, exp: []byte{0xde, 0xf3, 0xf, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x1000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 4096}, exp: []byte{0xde, 0x3, 0x10, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x2000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 8192}, exp: []byte{0xde, 0x3, 0x20, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x7ff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 32760}, exp: []byte{0xdb, 0x13, 0x40, 0x91, 0x7e, 0xfb, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xfff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 65520}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xf3, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffe8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 65512}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xeb, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0xffe0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 65504}, exp: []byte{0xdb, 0x33, 0x40, 0x91, 0x7e, 0xe3, 0x3f, 0xbd}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x8000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 134217728}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x40000000", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741824}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x40000008", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741832}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x3ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741816}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x40000010", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741840}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x3ffffff0", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 1073741808}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x7ffffff8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 2147483640}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/ConstOffset/src=V30,base=R30,offset=0x10000004", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstConst: 268435460}, exp: []byte{0x1b, 0x0, 0x0, 0x18, 0xde, 0x6b, 0x3b, 0xbc}}, {name: "FSTRS/RegisterOffset/src=V30,base=R30,offset=RegR8", n: &nodeImpl{instruction: FSTRS, srcReg: RegV30, dstReg: RegR30, dstReg2: RegR8}, exp: []byte{0xde, 0x6b, 0x28, 0xbc}}, } for _, tc := range tests { t.Run(tc.name, func(t *testing.T) { code := asm.CodeSegment{} defer func() { require.NoError(t, code.Unmap()) }() a := NewAssembler(RegR27) tc.n.types = operandTypesRegisterToMemory buf := code.NextCodeSection() err := a.encodeRegisterToMemory(buf, tc.n) require.NoError(t, err) err = a.Assemble(buf) require.NoError(t, err) actual := buf.Bytes() require.Equal(t, tc.exp, actual) }) } }