1 package arm64
2
3 import (
4 "encoding/hex"
5 "testing"
6
7 "github.com/tetratelabs/wazero/internal/asm"
8 "github.com/tetratelabs/wazero/internal/testing/require"
9 )
10
11 func TestAssemblerImpl_EncodeTwoRegistersToRegister(t *testing.T) {
12 t.Run("error", func(t *testing.T) {
13 tests := []struct {
14 n *nodeImpl
15 expErr string
16 }{
17 {
18 n: &nodeImpl{
19 instruction: ADR, types: operandTypesTwoRegistersToRegister,
20 srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0,
21 },
22 expErr: "ADR is unsupported for TwoRegistersToRegister type",
23 },
24 }
25
26 code := asm.CodeSegment{}
27 defer func() { require.NoError(t, code.Unmap()) }()
28
29 for _, tt := range tests {
30 tc := tt
31 a := NewAssembler(asm.NilRegister)
32 buf := code.NextCodeSection()
33 err := a.encodeTwoRegistersToRegister(buf, tc.n)
34 require.EqualError(t, err, tc.expErr)
35 }
36 })
37
38 tests := []struct {
39 name string
40 exp []byte
41 inst asm.Instruction
42 src asm.Register
43 src2 asm.Register
44 dst asm.Register
45 }{
46 {name: "src=RZR,src2=RZR,dst=RZR", inst: AND, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x8a}},
47 {name: "src=RZR,src2=RZR,dst=R10", inst: AND, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x8a}},
48 {name: "src=RZR,src2=RZR,dst=R30", inst: AND, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x8a}},
49 {name: "src=RZR,src2=R10,dst=RZR", inst: AND, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x8a}},
50 {name: "src=RZR,src2=R10,dst=R10", inst: AND, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x8a}},
51 {name: "src=RZR,src2=R10,dst=R30", inst: AND, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x8a}},
52 {name: "src=RZR,src2=R30,dst=RZR", inst: AND, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x8a}},
53 {name: "src=RZR,src2=R30,dst=R10", inst: AND, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x8a}},
54 {name: "src=RZR,src2=R30,dst=R30", inst: AND, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x8a}},
55 {name: "src=R10,src2=RZR,dst=RZR", inst: AND, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x8a}},
56 {name: "src=R10,src2=RZR,dst=R10", inst: AND, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x8a}},
57 {name: "src=R10,src2=RZR,dst=R30", inst: AND, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x8a}},
58 {name: "src=R10,src2=R10,dst=RZR", inst: AND, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x8a}},
59 {name: "src=R10,src2=R10,dst=R10", inst: AND, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x8a}},
60 {name: "src=R10,src2=R10,dst=R30", inst: AND, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x8a}},
61 {name: "src=R10,src2=R30,dst=RZR", inst: AND, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x8a}},
62 {name: "src=R10,src2=R30,dst=R10", inst: AND, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x8a}},
63 {name: "src=R10,src2=R30,dst=R30", inst: AND, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x8a}},
64 {name: "src=R30,src2=RZR,dst=RZR", inst: AND, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x8a}},
65 {name: "src=R30,src2=RZR,dst=R10", inst: AND, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x8a}},
66 {name: "src=R30,src2=RZR,dst=R30", inst: AND, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x8a}},
67 {name: "src=R30,src2=R10,dst=RZR", inst: AND, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x8a}},
68 {name: "src=R30,src2=R10,dst=R10", inst: AND, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x8a}},
69 {name: "src=R30,src2=R10,dst=R30", inst: AND, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x8a}},
70 {name: "src=R30,src2=R30,dst=RZR", inst: AND, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x8a}},
71 {name: "src=R30,src2=R30,dst=R10", inst: AND, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x8a}},
72 {name: "src=R30,src2=R30,dst=R30", inst: AND, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x8a}},
73 {name: "src=RZR,src2=RZR,dst=RZR", inst: ANDW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xa}},
74 {name: "src=RZR,src2=RZR,dst=R10", inst: ANDW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xa}},
75 {name: "src=RZR,src2=RZR,dst=R30", inst: ANDW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xa}},
76 {name: "src=RZR,src2=R10,dst=RZR", inst: ANDW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xa}},
77 {name: "src=RZR,src2=R10,dst=R10", inst: ANDW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xa}},
78 {name: "src=RZR,src2=R10,dst=R30", inst: ANDW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xa}},
79 {name: "src=RZR,src2=R30,dst=RZR", inst: ANDW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xa}},
80 {name: "src=RZR,src2=R30,dst=R10", inst: ANDW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xa}},
81 {name: "src=RZR,src2=R30,dst=R30", inst: ANDW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xa}},
82 {name: "src=R10,src2=RZR,dst=RZR", inst: ANDW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xa}},
83 {name: "src=R10,src2=RZR,dst=R10", inst: ANDW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xa}},
84 {name: "src=R10,src2=RZR,dst=R30", inst: ANDW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xa}},
85 {name: "src=R10,src2=R10,dst=RZR", inst: ANDW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xa}},
86 {name: "src=R10,src2=R10,dst=R10", inst: ANDW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xa}},
87 {name: "src=R10,src2=R10,dst=R30", inst: ANDW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xa}},
88 {name: "src=R10,src2=R30,dst=RZR", inst: ANDW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xa}},
89 {name: "src=R10,src2=R30,dst=R10", inst: ANDW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xa}},
90 {name: "src=R10,src2=R30,dst=R30", inst: ANDW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xa}},
91 {name: "src=R30,src2=RZR,dst=RZR", inst: ANDW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xa}},
92 {name: "src=R30,src2=RZR,dst=R10", inst: ANDW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xa}},
93 {name: "src=R30,src2=RZR,dst=R30", inst: ANDW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xa}},
94 {name: "src=R30,src2=R10,dst=RZR", inst: ANDW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xa}},
95 {name: "src=R30,src2=R10,dst=R10", inst: ANDW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xa}},
96 {name: "src=R30,src2=R10,dst=R30", inst: ANDW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xa}},
97 {name: "src=R30,src2=R30,dst=RZR", inst: ANDW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xa}},
98 {name: "src=R30,src2=R30,dst=R10", inst: ANDW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xa}},
99 {name: "src=R30,src2=R30,dst=R30", inst: ANDW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xa}},
100 {name: "src=RZR,src2=RZR,dst=RZR", inst: ORR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xaa}},
101 {name: "src=RZR,src2=RZR,dst=R10", inst: ORR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xaa}},
102 {name: "src=RZR,src2=RZR,dst=R30", inst: ORR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xaa}},
103 {name: "src=RZR,src2=R10,dst=RZR", inst: ORR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xaa}},
104 {name: "src=RZR,src2=R10,dst=R10", inst: ORR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xaa}},
105 {name: "src=RZR,src2=R10,dst=R30", inst: ORR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xaa}},
106 {name: "src=RZR,src2=R30,dst=RZR", inst: ORR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xaa}},
107 {name: "src=RZR,src2=R30,dst=R10", inst: ORR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xaa}},
108 {name: "src=RZR,src2=R30,dst=R30", inst: ORR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xaa}},
109 {name: "src=R10,src2=RZR,dst=RZR", inst: ORR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xaa}},
110 {name: "src=R10,src2=RZR,dst=R10", inst: ORR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xaa}},
111 {name: "src=R10,src2=RZR,dst=R30", inst: ORR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xaa}},
112 {name: "src=R10,src2=R10,dst=RZR", inst: ORR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xaa}},
113 {name: "src=R10,src2=R10,dst=R10", inst: ORR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xaa}},
114 {name: "src=R10,src2=R10,dst=R30", inst: ORR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xaa}},
115 {name: "src=R10,src2=R30,dst=RZR", inst: ORR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xaa}},
116 {name: "src=R10,src2=R30,dst=R10", inst: ORR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xaa}},
117 {name: "src=R10,src2=R30,dst=R30", inst: ORR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xaa}},
118 {name: "src=R30,src2=RZR,dst=RZR", inst: ORR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xaa}},
119 {name: "src=R30,src2=RZR,dst=R10", inst: ORR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xaa}},
120 {name: "src=R30,src2=RZR,dst=R30", inst: ORR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xaa}},
121 {name: "src=R30,src2=R10,dst=RZR", inst: ORR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xaa}},
122 {name: "src=R30,src2=R10,dst=R10", inst: ORR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xaa}},
123 {name: "src=R30,src2=R10,dst=R30", inst: ORR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xaa}},
124 {name: "src=R30,src2=R30,dst=RZR", inst: ORR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xaa}},
125 {name: "src=R30,src2=R30,dst=R10", inst: ORR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xaa}},
126 {name: "src=R30,src2=R30,dst=R30", inst: ORR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xaa}},
127 {name: "src=RZR,src2=RZR,dst=RZR", inst: ORRW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
128 {name: "src=RZR,src2=RZR,dst=R10", inst: ORRW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
129 {name: "src=RZR,src2=RZR,dst=R30", inst: ORRW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
130 {name: "src=RZR,src2=R10,dst=RZR", inst: ORRW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x2a}},
131 {name: "src=RZR,src2=R10,dst=R10", inst: ORRW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x2a}},
132 {name: "src=RZR,src2=R10,dst=R30", inst: ORRW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x2a}},
133 {name: "src=RZR,src2=R30,dst=RZR", inst: ORRW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x2a}},
134 {name: "src=RZR,src2=R30,dst=R10", inst: ORRW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x2a}},
135 {name: "src=RZR,src2=R30,dst=R30", inst: ORRW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x2a}},
136 {name: "src=R10,src2=RZR,dst=RZR", inst: ORRW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x2a}},
137 {name: "src=R10,src2=RZR,dst=R10", inst: ORRW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x2a}},
138 {name: "src=R10,src2=RZR,dst=R30", inst: ORRW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x2a}},
139 {name: "src=R10,src2=R10,dst=RZR", inst: ORRW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x2a}},
140 {name: "src=R10,src2=R10,dst=R10", inst: ORRW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x2a}},
141 {name: "src=R10,src2=R10,dst=R30", inst: ORRW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x2a}},
142 {name: "src=R10,src2=R30,dst=RZR", inst: ORRW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x2a}},
143 {name: "src=R10,src2=R30,dst=R10", inst: ORRW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x2a}},
144 {name: "src=R10,src2=R30,dst=R30", inst: ORRW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x2a}},
145 {name: "src=R30,src2=RZR,dst=RZR", inst: ORRW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x2a}},
146 {name: "src=R30,src2=RZR,dst=R10", inst: ORRW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x2a}},
147 {name: "src=R30,src2=RZR,dst=R30", inst: ORRW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x2a}},
148 {name: "src=R30,src2=R10,dst=RZR", inst: ORRW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x2a}},
149 {name: "src=R30,src2=R10,dst=R10", inst: ORRW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x2a}},
150 {name: "src=R30,src2=R10,dst=R30", inst: ORRW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x2a}},
151 {name: "src=R30,src2=R30,dst=RZR", inst: ORRW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x2a}},
152 {name: "src=R30,src2=R30,dst=R10", inst: ORRW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x2a}},
153 {name: "src=R30,src2=R30,dst=R30", inst: ORRW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x2a}},
154 {name: "src=RZR,src2=RZR,dst=RZR", inst: EOR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xca}},
155 {name: "src=RZR,src2=RZR,dst=R10", inst: EOR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xca}},
156 {name: "src=RZR,src2=RZR,dst=R30", inst: EOR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xca}},
157 {name: "src=RZR,src2=R10,dst=RZR", inst: EOR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xca}},
158 {name: "src=RZR,src2=R10,dst=R10", inst: EOR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xca}},
159 {name: "src=RZR,src2=R10,dst=R30", inst: EOR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xca}},
160 {name: "src=RZR,src2=R30,dst=RZR", inst: EOR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xca}},
161 {name: "src=RZR,src2=R30,dst=R10", inst: EOR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xca}},
162 {name: "src=RZR,src2=R30,dst=R30", inst: EOR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xca}},
163 {name: "src=R10,src2=RZR,dst=RZR", inst: EOR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xca}},
164 {name: "src=R10,src2=RZR,dst=R10", inst: EOR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xca}},
165 {name: "src=R10,src2=RZR,dst=R30", inst: EOR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xca}},
166 {name: "src=R10,src2=R10,dst=RZR", inst: EOR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xca}},
167 {name: "src=R10,src2=R10,dst=R10", inst: EOR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xca}},
168 {name: "src=R10,src2=R10,dst=R30", inst: EOR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xca}},
169 {name: "src=R10,src2=R30,dst=RZR", inst: EOR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xca}},
170 {name: "src=R10,src2=R30,dst=R10", inst: EOR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xca}},
171 {name: "src=R10,src2=R30,dst=R30", inst: EOR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xca}},
172 {name: "src=R30,src2=RZR,dst=RZR", inst: EOR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xca}},
173 {name: "src=R30,src2=RZR,dst=R10", inst: EOR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xca}},
174 {name: "src=R30,src2=RZR,dst=R30", inst: EOR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xca}},
175 {name: "src=R30,src2=R10,dst=RZR", inst: EOR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xca}},
176 {name: "src=R30,src2=R10,dst=R10", inst: EOR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xca}},
177 {name: "src=R30,src2=R10,dst=R30", inst: EOR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xca}},
178 {name: "src=R30,src2=R30,dst=RZR", inst: EOR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xca}},
179 {name: "src=R30,src2=R30,dst=R10", inst: EOR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xca}},
180 {name: "src=R30,src2=R30,dst=R30", inst: EOR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xca}},
181 {name: "src=RZR,src2=RZR,dst=RZR", inst: EORW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x4a}},
182 {name: "src=RZR,src2=RZR,dst=R10", inst: EORW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x4a}},
183 {name: "src=RZR,src2=RZR,dst=R30", inst: EORW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x4a}},
184 {name: "src=RZR,src2=R10,dst=RZR", inst: EORW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x4a}},
185 {name: "src=RZR,src2=R10,dst=R10", inst: EORW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x4a}},
186 {name: "src=RZR,src2=R10,dst=R30", inst: EORW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x4a}},
187 {name: "src=RZR,src2=R30,dst=RZR", inst: EORW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x4a}},
188 {name: "src=RZR,src2=R30,dst=R10", inst: EORW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x4a}},
189 {name: "src=RZR,src2=R30,dst=R30", inst: EORW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x4a}},
190 {name: "src=R10,src2=RZR,dst=RZR", inst: EORW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x4a}},
191 {name: "src=R10,src2=RZR,dst=R10", inst: EORW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x4a}},
192 {name: "src=R10,src2=RZR,dst=R30", inst: EORW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x4a}},
193 {name: "src=R10,src2=R10,dst=RZR", inst: EORW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x4a}},
194 {name: "src=R10,src2=R10,dst=R10", inst: EORW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x4a}},
195 {name: "src=R10,src2=R10,dst=R30", inst: EORW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x4a}},
196 {name: "src=R10,src2=R30,dst=RZR", inst: EORW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x4a}},
197 {name: "src=R10,src2=R30,dst=R10", inst: EORW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x4a}},
198 {name: "src=R10,src2=R30,dst=R30", inst: EORW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x4a}},
199 {name: "src=R30,src2=RZR,dst=RZR", inst: EORW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x4a}},
200 {name: "src=R30,src2=RZR,dst=R10", inst: EORW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x4a}},
201 {name: "src=R30,src2=RZR,dst=R30", inst: EORW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x4a}},
202 {name: "src=R30,src2=R10,dst=RZR", inst: EORW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x4a}},
203 {name: "src=R30,src2=R10,dst=R10", inst: EORW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x4a}},
204 {name: "src=R30,src2=R10,dst=R30", inst: EORW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x4a}},
205 {name: "src=R30,src2=R30,dst=RZR", inst: EORW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x4a}},
206 {name: "src=R30,src2=R30,dst=R10", inst: EORW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x4a}},
207 {name: "src=R30,src2=R30,dst=R30", inst: EORW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x4a}},
208 {name: "src=RZR,src2=RZR,dst=RZR", inst: ASR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xdf, 0x9a}},
209 {name: "src=RZR,src2=RZR,dst=R10", inst: ASR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xdf, 0x9a}},
210 {name: "src=RZR,src2=RZR,dst=R30", inst: ASR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xdf, 0x9a}},
211 {name: "src=RZR,src2=R10,dst=RZR", inst: ASR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xdf, 0x9a}},
212 {name: "src=RZR,src2=R10,dst=R10", inst: ASR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xdf, 0x9a}},
213 {name: "src=RZR,src2=R10,dst=R30", inst: ASR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xdf, 0x9a}},
214 {name: "src=RZR,src2=R30,dst=RZR", inst: ASR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xdf, 0x9a}},
215 {name: "src=RZR,src2=R30,dst=R10", inst: ASR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xdf, 0x9a}},
216 {name: "src=RZR,src2=R30,dst=R30", inst: ASR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xdf, 0x9a}},
217 {name: "src=R10,src2=RZR,dst=RZR", inst: ASR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xca, 0x9a}},
218 {name: "src=R10,src2=RZR,dst=R10", inst: ASR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xca, 0x9a}},
219 {name: "src=R10,src2=RZR,dst=R30", inst: ASR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xca, 0x9a}},
220 {name: "src=R10,src2=R10,dst=RZR", inst: ASR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xca, 0x9a}},
221 {name: "src=R10,src2=R10,dst=R10", inst: ASR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xca, 0x9a}},
222 {name: "src=R10,src2=R10,dst=R30", inst: ASR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xca, 0x9a}},
223 {name: "src=R10,src2=R30,dst=RZR", inst: ASR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xca, 0x9a}},
224 {name: "src=R10,src2=R30,dst=R10", inst: ASR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xca, 0x9a}},
225 {name: "src=R10,src2=R30,dst=R30", inst: ASR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xca, 0x9a}},
226 {name: "src=R30,src2=RZR,dst=RZR", inst: ASR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xde, 0x9a}},
227 {name: "src=R30,src2=RZR,dst=R10", inst: ASR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xde, 0x9a}},
228 {name: "src=R30,src2=RZR,dst=R30", inst: ASR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xde, 0x9a}},
229 {name: "src=R30,src2=R10,dst=RZR", inst: ASR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xde, 0x9a}},
230 {name: "src=R30,src2=R10,dst=R10", inst: ASR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xde, 0x9a}},
231 {name: "src=R30,src2=R10,dst=R30", inst: ASR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xde, 0x9a}},
232 {name: "src=R30,src2=R30,dst=RZR", inst: ASR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xde, 0x9a}},
233 {name: "src=R30,src2=R30,dst=R10", inst: ASR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xde, 0x9a}},
234 {name: "src=R30,src2=R30,dst=R30", inst: ASR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xde, 0x9a}},
235 {name: "src=RZR,src2=RZR,dst=RZR", inst: ASRW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xdf, 0x1a}},
236 {name: "src=RZR,src2=RZR,dst=R10", inst: ASRW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xdf, 0x1a}},
237 {name: "src=RZR,src2=RZR,dst=R30", inst: ASRW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xdf, 0x1a}},
238 {name: "src=RZR,src2=R10,dst=RZR", inst: ASRW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xdf, 0x1a}},
239 {name: "src=RZR,src2=R10,dst=R10", inst: ASRW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xdf, 0x1a}},
240 {name: "src=RZR,src2=R10,dst=R30", inst: ASRW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xdf, 0x1a}},
241 {name: "src=RZR,src2=R30,dst=RZR", inst: ASRW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xdf, 0x1a}},
242 {name: "src=RZR,src2=R30,dst=R10", inst: ASRW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xdf, 0x1a}},
243 {name: "src=RZR,src2=R30,dst=R30", inst: ASRW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xdf, 0x1a}},
244 {name: "src=R10,src2=RZR,dst=RZR", inst: ASRW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xca, 0x1a}},
245 {name: "src=R10,src2=RZR,dst=R10", inst: ASRW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xca, 0x1a}},
246 {name: "src=R10,src2=RZR,dst=R30", inst: ASRW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xca, 0x1a}},
247 {name: "src=R10,src2=R10,dst=RZR", inst: ASRW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xca, 0x1a}},
248 {name: "src=R10,src2=R10,dst=R10", inst: ASRW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xca, 0x1a}},
249 {name: "src=R10,src2=R10,dst=R30", inst: ASRW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xca, 0x1a}},
250 {name: "src=R10,src2=R30,dst=RZR", inst: ASRW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xca, 0x1a}},
251 {name: "src=R10,src2=R30,dst=R10", inst: ASRW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xca, 0x1a}},
252 {name: "src=R10,src2=R30,dst=R30", inst: ASRW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xca, 0x1a}},
253 {name: "src=R30,src2=RZR,dst=RZR", inst: ASRW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xde, 0x1a}},
254 {name: "src=R30,src2=RZR,dst=R10", inst: ASRW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xde, 0x1a}},
255 {name: "src=R30,src2=RZR,dst=R30", inst: ASRW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xde, 0x1a}},
256 {name: "src=R30,src2=R10,dst=RZR", inst: ASRW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xde, 0x1a}},
257 {name: "src=R30,src2=R10,dst=R10", inst: ASRW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xde, 0x1a}},
258 {name: "src=R30,src2=R10,dst=R30", inst: ASRW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xde, 0x1a}},
259 {name: "src=R30,src2=R30,dst=RZR", inst: ASRW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xde, 0x1a}},
260 {name: "src=R30,src2=R30,dst=R10", inst: ASRW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xde, 0x1a}},
261 {name: "src=R30,src2=R30,dst=R30", inst: ASRW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xde, 0x1a}},
262 {name: "src=RZR,src2=RZR,dst=RZR", inst: LSL, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xdf, 0x9a}},
263 {name: "src=RZR,src2=RZR,dst=R10", inst: LSL, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xdf, 0x9a}},
264 {name: "src=RZR,src2=RZR,dst=R30", inst: LSL, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xdf, 0x9a}},
265 {name: "src=RZR,src2=R10,dst=RZR", inst: LSL, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xdf, 0x9a}},
266 {name: "src=RZR,src2=R10,dst=R10", inst: LSL, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xdf, 0x9a}},
267 {name: "src=RZR,src2=R10,dst=R30", inst: LSL, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xdf, 0x9a}},
268 {name: "src=RZR,src2=R30,dst=RZR", inst: LSL, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xdf, 0x9a}},
269 {name: "src=RZR,src2=R30,dst=R10", inst: LSL, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xdf, 0x9a}},
270 {name: "src=RZR,src2=R30,dst=R30", inst: LSL, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xdf, 0x9a}},
271 {name: "src=R10,src2=RZR,dst=RZR", inst: LSL, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xca, 0x9a}},
272 {name: "src=R10,src2=RZR,dst=R10", inst: LSL, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xca, 0x9a}},
273 {name: "src=R10,src2=RZR,dst=R30", inst: LSL, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xca, 0x9a}},
274 {name: "src=R10,src2=R10,dst=RZR", inst: LSL, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xca, 0x9a}},
275 {name: "src=R10,src2=R10,dst=R10", inst: LSL, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xca, 0x9a}},
276 {name: "src=R10,src2=R10,dst=R30", inst: LSL, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xca, 0x9a}},
277 {name: "src=R10,src2=R30,dst=RZR", inst: LSL, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xca, 0x9a}},
278 {name: "src=R10,src2=R30,dst=R10", inst: LSL, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xca, 0x9a}},
279 {name: "src=R10,src2=R30,dst=R30", inst: LSL, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xca, 0x9a}},
280 {name: "src=R30,src2=RZR,dst=RZR", inst: LSL, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xde, 0x9a}},
281 {name: "src=R30,src2=RZR,dst=R10", inst: LSL, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xde, 0x9a}},
282 {name: "src=R30,src2=RZR,dst=R30", inst: LSL, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xde, 0x9a}},
283 {name: "src=R30,src2=R10,dst=RZR", inst: LSL, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xde, 0x9a}},
284 {name: "src=R30,src2=R10,dst=R10", inst: LSL, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xde, 0x9a}},
285 {name: "src=R30,src2=R10,dst=R30", inst: LSL, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xde, 0x9a}},
286 {name: "src=R30,src2=R30,dst=RZR", inst: LSL, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xde, 0x9a}},
287 {name: "src=R30,src2=R30,dst=R10", inst: LSL, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xde, 0x9a}},
288 {name: "src=R30,src2=R30,dst=R30", inst: LSL, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xde, 0x9a}},
289 {name: "src=RZR,src2=RZR,dst=RZR", inst: LSLW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xdf, 0x1a}},
290 {name: "src=RZR,src2=RZR,dst=R10", inst: LSLW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xdf, 0x1a}},
291 {name: "src=RZR,src2=RZR,dst=R30", inst: LSLW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xdf, 0x1a}},
292 {name: "src=RZR,src2=R10,dst=RZR", inst: LSLW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xdf, 0x1a}},
293 {name: "src=RZR,src2=R10,dst=R10", inst: LSLW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xdf, 0x1a}},
294 {name: "src=RZR,src2=R10,dst=R30", inst: LSLW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xdf, 0x1a}},
295 {name: "src=RZR,src2=R30,dst=RZR", inst: LSLW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xdf, 0x1a}},
296 {name: "src=RZR,src2=R30,dst=R10", inst: LSLW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xdf, 0x1a}},
297 {name: "src=RZR,src2=R30,dst=R30", inst: LSLW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xdf, 0x1a}},
298 {name: "src=R10,src2=RZR,dst=RZR", inst: LSLW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xca, 0x1a}},
299 {name: "src=R10,src2=RZR,dst=R10", inst: LSLW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xca, 0x1a}},
300 {name: "src=R10,src2=RZR,dst=R30", inst: LSLW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xca, 0x1a}},
301 {name: "src=R10,src2=R10,dst=RZR", inst: LSLW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xca, 0x1a}},
302 {name: "src=R10,src2=R10,dst=R10", inst: LSLW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xca, 0x1a}},
303 {name: "src=R10,src2=R10,dst=R30", inst: LSLW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xca, 0x1a}},
304 {name: "src=R10,src2=R30,dst=RZR", inst: LSLW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xca, 0x1a}},
305 {name: "src=R10,src2=R30,dst=R10", inst: LSLW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xca, 0x1a}},
306 {name: "src=R10,src2=R30,dst=R30", inst: LSLW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xca, 0x1a}},
307 {name: "src=R30,src2=RZR,dst=RZR", inst: LSLW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xde, 0x1a}},
308 {name: "src=R30,src2=RZR,dst=R10", inst: LSLW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xde, 0x1a}},
309 {name: "src=R30,src2=RZR,dst=R30", inst: LSLW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xde, 0x1a}},
310 {name: "src=R30,src2=R10,dst=RZR", inst: LSLW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xde, 0x1a}},
311 {name: "src=R30,src2=R10,dst=R10", inst: LSLW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xde, 0x1a}},
312 {name: "src=R30,src2=R10,dst=R30", inst: LSLW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xde, 0x1a}},
313 {name: "src=R30,src2=R30,dst=RZR", inst: LSLW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xde, 0x1a}},
314 {name: "src=R30,src2=R30,dst=R10", inst: LSLW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xde, 0x1a}},
315 {name: "src=R30,src2=R30,dst=R30", inst: LSLW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xde, 0x1a}},
316 {name: "src=RZR,src2=RZR,dst=RZR", inst: LSR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xdf, 0x9a}},
317 {name: "src=RZR,src2=RZR,dst=R10", inst: LSR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xdf, 0x9a}},
318 {name: "src=RZR,src2=RZR,dst=R30", inst: LSR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xdf, 0x9a}},
319 {name: "src=RZR,src2=R10,dst=RZR", inst: LSR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xdf, 0x9a}},
320 {name: "src=RZR,src2=R10,dst=R10", inst: LSR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xdf, 0x9a}},
321 {name: "src=RZR,src2=R10,dst=R30", inst: LSR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xdf, 0x9a}},
322 {name: "src=RZR,src2=R30,dst=RZR", inst: LSR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xdf, 0x9a}},
323 {name: "src=RZR,src2=R30,dst=R10", inst: LSR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xdf, 0x9a}},
324 {name: "src=RZR,src2=R30,dst=R30", inst: LSR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xdf, 0x9a}},
325 {name: "src=R10,src2=RZR,dst=RZR", inst: LSR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xca, 0x9a}},
326 {name: "src=R10,src2=RZR,dst=R10", inst: LSR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xca, 0x9a}},
327 {name: "src=R10,src2=RZR,dst=R30", inst: LSR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xca, 0x9a}},
328 {name: "src=R10,src2=R10,dst=RZR", inst: LSR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xca, 0x9a}},
329 {name: "src=R10,src2=R10,dst=R10", inst: LSR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xca, 0x9a}},
330 {name: "src=R10,src2=R10,dst=R30", inst: LSR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xca, 0x9a}},
331 {name: "src=R10,src2=R30,dst=RZR", inst: LSR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xca, 0x9a}},
332 {name: "src=R10,src2=R30,dst=R10", inst: LSR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xca, 0x9a}},
333 {name: "src=R10,src2=R30,dst=R30", inst: LSR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xca, 0x9a}},
334 {name: "src=R30,src2=RZR,dst=RZR", inst: LSR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xde, 0x9a}},
335 {name: "src=R30,src2=RZR,dst=R10", inst: LSR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xde, 0x9a}},
336 {name: "src=R30,src2=RZR,dst=R30", inst: LSR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xde, 0x9a}},
337 {name: "src=R30,src2=R10,dst=RZR", inst: LSR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xde, 0x9a}},
338 {name: "src=R30,src2=R10,dst=R10", inst: LSR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xde, 0x9a}},
339 {name: "src=R30,src2=R10,dst=R30", inst: LSR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xde, 0x9a}},
340 {name: "src=R30,src2=R30,dst=RZR", inst: LSR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xde, 0x9a}},
341 {name: "src=R30,src2=R30,dst=R10", inst: LSR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xde, 0x9a}},
342 {name: "src=R30,src2=R30,dst=R30", inst: LSR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xde, 0x9a}},
343 {name: "src=RZR,src2=RZR,dst=RZR", inst: LSRW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xdf, 0x1a}},
344 {name: "src=RZR,src2=RZR,dst=R10", inst: LSRW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xdf, 0x1a}},
345 {name: "src=RZR,src2=RZR,dst=R30", inst: LSRW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xdf, 0x1a}},
346 {name: "src=RZR,src2=R10,dst=RZR", inst: LSRW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xdf, 0x1a}},
347 {name: "src=RZR,src2=R10,dst=R10", inst: LSRW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xdf, 0x1a}},
348 {name: "src=RZR,src2=R10,dst=R30", inst: LSRW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xdf, 0x1a}},
349 {name: "src=RZR,src2=R30,dst=RZR", inst: LSRW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xdf, 0x1a}},
350 {name: "src=RZR,src2=R30,dst=R10", inst: LSRW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xdf, 0x1a}},
351 {name: "src=RZR,src2=R30,dst=R30", inst: LSRW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xdf, 0x1a}},
352 {name: "src=R10,src2=RZR,dst=RZR", inst: LSRW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xca, 0x1a}},
353 {name: "src=R10,src2=RZR,dst=R10", inst: LSRW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xca, 0x1a}},
354 {name: "src=R10,src2=RZR,dst=R30", inst: LSRW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xca, 0x1a}},
355 {name: "src=R10,src2=R10,dst=RZR", inst: LSRW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xca, 0x1a}},
356 {name: "src=R10,src2=R10,dst=R10", inst: LSRW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xca, 0x1a}},
357 {name: "src=R10,src2=R10,dst=R30", inst: LSRW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xca, 0x1a}},
358 {name: "src=R10,src2=R30,dst=RZR", inst: LSRW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xca, 0x1a}},
359 {name: "src=R10,src2=R30,dst=R10", inst: LSRW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xca, 0x1a}},
360 {name: "src=R10,src2=R30,dst=R30", inst: LSRW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xca, 0x1a}},
361 {name: "src=R30,src2=RZR,dst=RZR", inst: LSRW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xde, 0x1a}},
362 {name: "src=R30,src2=RZR,dst=R10", inst: LSRW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xde, 0x1a}},
363 {name: "src=R30,src2=RZR,dst=R30", inst: LSRW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xde, 0x1a}},
364 {name: "src=R30,src2=R10,dst=RZR", inst: LSRW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xde, 0x1a}},
365 {name: "src=R30,src2=R10,dst=R10", inst: LSRW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xde, 0x1a}},
366 {name: "src=R30,src2=R10,dst=R30", inst: LSRW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xde, 0x1a}},
367 {name: "src=R30,src2=R30,dst=RZR", inst: LSRW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xde, 0x1a}},
368 {name: "src=R30,src2=R30,dst=R10", inst: LSRW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xde, 0x1a}},
369 {name: "src=R30,src2=R30,dst=R30", inst: LSRW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xde, 0x1a}},
370 {name: "src=RZR,src2=RZR,dst=RZR", inst: ROR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xdf, 0x9a}},
371 {name: "src=RZR,src2=RZR,dst=R10", inst: ROR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xdf, 0x9a}},
372 {name: "src=RZR,src2=RZR,dst=R30", inst: ROR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xdf, 0x9a}},
373 {name: "src=RZR,src2=R10,dst=RZR", inst: ROR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xdf, 0x9a}},
374 {name: "src=RZR,src2=R10,dst=R10", inst: ROR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xdf, 0x9a}},
375 {name: "src=RZR,src2=R10,dst=R30", inst: ROR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xdf, 0x9a}},
376 {name: "src=RZR,src2=R30,dst=RZR", inst: ROR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xdf, 0x9a}},
377 {name: "src=RZR,src2=R30,dst=R10", inst: ROR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xdf, 0x9a}},
378 {name: "src=RZR,src2=R30,dst=R30", inst: ROR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xdf, 0x9a}},
379 {name: "src=R10,src2=RZR,dst=RZR", inst: ROR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xca, 0x9a}},
380 {name: "src=R10,src2=RZR,dst=R10", inst: ROR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xca, 0x9a}},
381 {name: "src=R10,src2=RZR,dst=R30", inst: ROR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xca, 0x9a}},
382 {name: "src=R10,src2=R10,dst=RZR", inst: ROR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xca, 0x9a}},
383 {name: "src=R10,src2=R10,dst=R10", inst: ROR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xca, 0x9a}},
384 {name: "src=R10,src2=R10,dst=R30", inst: ROR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xca, 0x9a}},
385 {name: "src=R10,src2=R30,dst=RZR", inst: ROR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xca, 0x9a}},
386 {name: "src=R10,src2=R30,dst=R10", inst: ROR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xca, 0x9a}},
387 {name: "src=R10,src2=R30,dst=R30", inst: ROR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xca, 0x9a}},
388 {name: "src=R30,src2=RZR,dst=RZR", inst: ROR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xde, 0x9a}},
389 {name: "src=R30,src2=RZR,dst=R10", inst: ROR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xde, 0x9a}},
390 {name: "src=R30,src2=RZR,dst=R30", inst: ROR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xde, 0x9a}},
391 {name: "src=R30,src2=R10,dst=RZR", inst: ROR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xde, 0x9a}},
392 {name: "src=R30,src2=R10,dst=R10", inst: ROR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xde, 0x9a}},
393 {name: "src=R30,src2=R10,dst=R30", inst: ROR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xde, 0x9a}},
394 {name: "src=R30,src2=R30,dst=RZR", inst: ROR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xde, 0x9a}},
395 {name: "src=R30,src2=R30,dst=R10", inst: ROR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xde, 0x9a}},
396 {name: "src=R30,src2=R30,dst=R30", inst: ROR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xde, 0x9a}},
397 {name: "src=RZR,src2=RZR,dst=RZR", inst: RORW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xdf, 0x1a}},
398 {name: "src=RZR,src2=RZR,dst=R10", inst: RORW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xdf, 0x1a}},
399 {name: "src=RZR,src2=RZR,dst=R30", inst: RORW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xdf, 0x1a}},
400 {name: "src=RZR,src2=R10,dst=RZR", inst: RORW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xdf, 0x1a}},
401 {name: "src=RZR,src2=R10,dst=R10", inst: RORW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xdf, 0x1a}},
402 {name: "src=RZR,src2=R10,dst=R30", inst: RORW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xdf, 0x1a}},
403 {name: "src=RZR,src2=R30,dst=RZR", inst: RORW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xdf, 0x1a}},
404 {name: "src=RZR,src2=R30,dst=R10", inst: RORW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xdf, 0x1a}},
405 {name: "src=RZR,src2=R30,dst=R30", inst: RORW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xdf, 0x1a}},
406 {name: "src=R10,src2=RZR,dst=RZR", inst: RORW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xca, 0x1a}},
407 {name: "src=R10,src2=RZR,dst=R10", inst: RORW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xca, 0x1a}},
408 {name: "src=R10,src2=RZR,dst=R30", inst: RORW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xca, 0x1a}},
409 {name: "src=R10,src2=R10,dst=RZR", inst: RORW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xca, 0x1a}},
410 {name: "src=R10,src2=R10,dst=R10", inst: RORW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xca, 0x1a}},
411 {name: "src=R10,src2=R10,dst=R30", inst: RORW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xca, 0x1a}},
412 {name: "src=R10,src2=R30,dst=RZR", inst: RORW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xca, 0x1a}},
413 {name: "src=R10,src2=R30,dst=R10", inst: RORW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xca, 0x1a}},
414 {name: "src=R10,src2=R30,dst=R30", inst: RORW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xca, 0x1a}},
415 {name: "src=R30,src2=RZR,dst=RZR", inst: RORW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xde, 0x1a}},
416 {name: "src=R30,src2=RZR,dst=R10", inst: RORW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xde, 0x1a}},
417 {name: "src=R30,src2=RZR,dst=R30", inst: RORW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xde, 0x1a}},
418 {name: "src=R30,src2=R10,dst=RZR", inst: RORW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xde, 0x1a}},
419 {name: "src=R30,src2=R10,dst=R10", inst: RORW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xde, 0x1a}},
420 {name: "src=R30,src2=R10,dst=R30", inst: RORW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xde, 0x1a}},
421 {name: "src=R30,src2=R30,dst=RZR", inst: RORW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xde, 0x1a}},
422 {name: "src=R30,src2=R30,dst=R10", inst: RORW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xde, 0x1a}},
423 {name: "src=R30,src2=R30,dst=R30", inst: RORW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xde, 0x1a}},
424 {name: "src=RZR,src2=RZR,dst=RZR", inst: SDIV, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x9a}},
425 {name: "src=RZR,src2=RZR,dst=R10", inst: SDIV, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xdf, 0x9a}},
426 {name: "src=RZR,src2=RZR,dst=R30", inst: SDIV, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xdf, 0x9a}},
427 {name: "src=RZR,src2=R10,dst=RZR", inst: SDIV, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xdf, 0x9a}},
428 {name: "src=RZR,src2=R10,dst=R10", inst: SDIV, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x9a}},
429 {name: "src=RZR,src2=R10,dst=R30", inst: SDIV, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xdf, 0x9a}},
430 {name: "src=RZR,src2=R30,dst=RZR", inst: SDIV, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xdf, 0x9a}},
431 {name: "src=RZR,src2=R30,dst=R10", inst: SDIV, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xdf, 0x9a}},
432 {name: "src=RZR,src2=R30,dst=R30", inst: SDIV, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x9a}},
433 {name: "src=R10,src2=RZR,dst=RZR", inst: SDIV, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x9a}},
434 {name: "src=R10,src2=RZR,dst=R10", inst: SDIV, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xca, 0x9a}},
435 {name: "src=R10,src2=RZR,dst=R30", inst: SDIV, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xca, 0x9a}},
436 {name: "src=R10,src2=R10,dst=RZR", inst: SDIV, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xca, 0x9a}},
437 {name: "src=R10,src2=R10,dst=R10", inst: SDIV, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x9a}},
438 {name: "src=R10,src2=R10,dst=R30", inst: SDIV, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xca, 0x9a}},
439 {name: "src=R10,src2=R30,dst=RZR", inst: SDIV, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xca, 0x9a}},
440 {name: "src=R10,src2=R30,dst=R10", inst: SDIV, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xca, 0x9a}},
441 {name: "src=R10,src2=R30,dst=R30", inst: SDIV, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x9a}},
442 {name: "src=R30,src2=RZR,dst=RZR", inst: SDIV, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x9a}},
443 {name: "src=R30,src2=RZR,dst=R10", inst: SDIV, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xde, 0x9a}},
444 {name: "src=R30,src2=RZR,dst=R30", inst: SDIV, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xde, 0x9a}},
445 {name: "src=R30,src2=R10,dst=RZR", inst: SDIV, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xde, 0x9a}},
446 {name: "src=R30,src2=R10,dst=R10", inst: SDIV, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x9a}},
447 {name: "src=R30,src2=R10,dst=R30", inst: SDIV, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xde, 0x9a}},
448 {name: "src=R30,src2=R30,dst=RZR", inst: SDIV, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xde, 0x9a}},
449 {name: "src=R30,src2=R30,dst=R10", inst: SDIV, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xde, 0x9a}},
450 {name: "src=R30,src2=R30,dst=R30", inst: SDIV, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x9a}},
451 {name: "src=RZR,src2=RZR,dst=RZR", inst: SDIVW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x1a}},
452 {name: "src=RZR,src2=RZR,dst=R10", inst: SDIVW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xdf, 0x1a}},
453 {name: "src=RZR,src2=RZR,dst=R30", inst: SDIVW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xdf, 0x1a}},
454 {name: "src=RZR,src2=R10,dst=RZR", inst: SDIVW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xdf, 0x1a}},
455 {name: "src=RZR,src2=R10,dst=R10", inst: SDIVW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x1a}},
456 {name: "src=RZR,src2=R10,dst=R30", inst: SDIVW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xdf, 0x1a}},
457 {name: "src=RZR,src2=R30,dst=RZR", inst: SDIVW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xdf, 0x1a}},
458 {name: "src=RZR,src2=R30,dst=R10", inst: SDIVW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xdf, 0x1a}},
459 {name: "src=RZR,src2=R30,dst=R30", inst: SDIVW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x1a}},
460 {name: "src=R10,src2=RZR,dst=RZR", inst: SDIVW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x1a}},
461 {name: "src=R10,src2=RZR,dst=R10", inst: SDIVW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xca, 0x1a}},
462 {name: "src=R10,src2=RZR,dst=R30", inst: SDIVW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xca, 0x1a}},
463 {name: "src=R10,src2=R10,dst=RZR", inst: SDIVW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xca, 0x1a}},
464 {name: "src=R10,src2=R10,dst=R10", inst: SDIVW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x1a}},
465 {name: "src=R10,src2=R10,dst=R30", inst: SDIVW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xca, 0x1a}},
466 {name: "src=R10,src2=R30,dst=RZR", inst: SDIVW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xca, 0x1a}},
467 {name: "src=R10,src2=R30,dst=R10", inst: SDIVW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xca, 0x1a}},
468 {name: "src=R10,src2=R30,dst=R30", inst: SDIVW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x1a}},
469 {name: "src=R30,src2=RZR,dst=RZR", inst: SDIVW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x1a}},
470 {name: "src=R30,src2=RZR,dst=R10", inst: SDIVW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xde, 0x1a}},
471 {name: "src=R30,src2=RZR,dst=R30", inst: SDIVW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xde, 0x1a}},
472 {name: "src=R30,src2=R10,dst=RZR", inst: SDIVW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xde, 0x1a}},
473 {name: "src=R30,src2=R10,dst=R10", inst: SDIVW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x1a}},
474 {name: "src=R30,src2=R10,dst=R30", inst: SDIVW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xde, 0x1a}},
475 {name: "src=R30,src2=R30,dst=RZR", inst: SDIVW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xde, 0x1a}},
476 {name: "src=R30,src2=R30,dst=R10", inst: SDIVW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xde, 0x1a}},
477 {name: "src=R30,src2=R30,dst=R30", inst: SDIVW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x1a}},
478 {name: "src=RZR,src2=RZR,dst=RZR", inst: UDIV, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x9a}},
479 {name: "src=RZR,src2=RZR,dst=R10", inst: UDIV, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xdf, 0x9a}},
480 {name: "src=RZR,src2=RZR,dst=R30", inst: UDIV, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xdf, 0x9a}},
481 {name: "src=RZR,src2=R10,dst=RZR", inst: UDIV, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xdf, 0x9a}},
482 {name: "src=RZR,src2=R10,dst=R10", inst: UDIV, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x9a}},
483 {name: "src=RZR,src2=R10,dst=R30", inst: UDIV, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xdf, 0x9a}},
484 {name: "src=RZR,src2=R30,dst=RZR", inst: UDIV, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xdf, 0x9a}},
485 {name: "src=RZR,src2=R30,dst=R10", inst: UDIV, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xdf, 0x9a}},
486 {name: "src=RZR,src2=R30,dst=R30", inst: UDIV, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x9a}},
487 {name: "src=R10,src2=RZR,dst=RZR", inst: UDIV, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x9a}},
488 {name: "src=R10,src2=RZR,dst=R10", inst: UDIV, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xca, 0x9a}},
489 {name: "src=R10,src2=RZR,dst=R30", inst: UDIV, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xca, 0x9a}},
490 {name: "src=R10,src2=R10,dst=RZR", inst: UDIV, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xca, 0x9a}},
491 {name: "src=R10,src2=R10,dst=R10", inst: UDIV, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x9a}},
492 {name: "src=R10,src2=R10,dst=R30", inst: UDIV, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xca, 0x9a}},
493 {name: "src=R10,src2=R30,dst=RZR", inst: UDIV, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xca, 0x9a}},
494 {name: "src=R10,src2=R30,dst=R10", inst: UDIV, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xca, 0x9a}},
495 {name: "src=R10,src2=R30,dst=R30", inst: UDIV, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x9a}},
496 {name: "src=R30,src2=RZR,dst=RZR", inst: UDIV, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x9a}},
497 {name: "src=R30,src2=RZR,dst=R10", inst: UDIV, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xde, 0x9a}},
498 {name: "src=R30,src2=RZR,dst=R30", inst: UDIV, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xde, 0x9a}},
499 {name: "src=R30,src2=R10,dst=RZR", inst: UDIV, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xde, 0x9a}},
500 {name: "src=R30,src2=R10,dst=R10", inst: UDIV, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x9a}},
501 {name: "src=R30,src2=R10,dst=R30", inst: UDIV, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xde, 0x9a}},
502 {name: "src=R30,src2=R30,dst=RZR", inst: UDIV, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xde, 0x9a}},
503 {name: "src=R30,src2=R30,dst=R10", inst: UDIV, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xde, 0x9a}},
504 {name: "src=R30,src2=R30,dst=R30", inst: UDIV, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x9a}},
505 {name: "src=RZR,src2=RZR,dst=RZR", inst: UDIVW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x1a}},
506 {name: "src=RZR,src2=RZR,dst=R10", inst: UDIVW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xdf, 0x1a}},
507 {name: "src=RZR,src2=RZR,dst=R30", inst: UDIVW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xdf, 0x1a}},
508 {name: "src=RZR,src2=R10,dst=RZR", inst: UDIVW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xdf, 0x1a}},
509 {name: "src=RZR,src2=R10,dst=R10", inst: UDIVW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x1a}},
510 {name: "src=RZR,src2=R10,dst=R30", inst: UDIVW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xdf, 0x1a}},
511 {name: "src=RZR,src2=R30,dst=RZR", inst: UDIVW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xdf, 0x1a}},
512 {name: "src=RZR,src2=R30,dst=R10", inst: UDIVW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xdf, 0x1a}},
513 {name: "src=RZR,src2=R30,dst=R30", inst: UDIVW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x1a}},
514 {name: "src=R10,src2=RZR,dst=RZR", inst: UDIVW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x1a}},
515 {name: "src=R10,src2=RZR,dst=R10", inst: UDIVW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xca, 0x1a}},
516 {name: "src=R10,src2=RZR,dst=R30", inst: UDIVW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xca, 0x1a}},
517 {name: "src=R10,src2=R10,dst=RZR", inst: UDIVW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xca, 0x1a}},
518 {name: "src=R10,src2=R10,dst=R10", inst: UDIVW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x1a}},
519 {name: "src=R10,src2=R10,dst=R30", inst: UDIVW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xca, 0x1a}},
520 {name: "src=R10,src2=R30,dst=RZR", inst: UDIVW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xca, 0x1a}},
521 {name: "src=R10,src2=R30,dst=R10", inst: UDIVW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xca, 0x1a}},
522 {name: "src=R10,src2=R30,dst=R30", inst: UDIVW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x1a}},
523 {name: "src=R30,src2=RZR,dst=RZR", inst: UDIVW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x1a}},
524 {name: "src=R30,src2=RZR,dst=R10", inst: UDIVW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xde, 0x1a}},
525 {name: "src=R30,src2=RZR,dst=R30", inst: UDIVW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xde, 0x1a}},
526 {name: "src=R30,src2=R10,dst=RZR", inst: UDIVW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xde, 0x1a}},
527 {name: "src=R30,src2=R10,dst=R10", inst: UDIVW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x1a}},
528 {name: "src=R30,src2=R10,dst=R30", inst: UDIVW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xde, 0x1a}},
529 {name: "src=R30,src2=R30,dst=RZR", inst: UDIVW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xde, 0x1a}},
530 {name: "src=R30,src2=R30,dst=R10", inst: UDIVW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xde, 0x1a}},
531 {name: "src=R30,src2=R30,dst=R30", inst: UDIVW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x1a}},
532 {name: "src=RZR,src2=RZR,dst=RZR", inst: SUB, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xcb}},
533 {name: "src=RZR,src2=RZR,dst=R10", inst: SUB, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xcb}},
534 {name: "src=RZR,src2=RZR,dst=R30", inst: SUB, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xcb}},
535 {name: "src=RZR,src2=R10,dst=RZR", inst: SUB, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xcb}},
536 {name: "src=RZR,src2=R10,dst=R10", inst: SUB, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xcb}},
537 {name: "src=RZR,src2=R10,dst=R30", inst: SUB, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xcb}},
538 {name: "src=RZR,src2=R30,dst=RZR", inst: SUB, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xcb}},
539 {name: "src=RZR,src2=R30,dst=R10", inst: SUB, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xcb}},
540 {name: "src=RZR,src2=R30,dst=R30", inst: SUB, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xcb}},
541 {name: "src=R10,src2=RZR,dst=RZR", inst: SUB, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xcb}},
542 {name: "src=R10,src2=RZR,dst=R10", inst: SUB, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xcb}},
543 {name: "src=R10,src2=RZR,dst=R30", inst: SUB, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xcb}},
544 {name: "src=R10,src2=R10,dst=RZR", inst: SUB, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xcb}},
545 {name: "src=R10,src2=R10,dst=R10", inst: SUB, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xcb}},
546 {name: "src=R10,src2=R10,dst=R30", inst: SUB, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xcb}},
547 {name: "src=R10,src2=R30,dst=RZR", inst: SUB, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xcb}},
548 {name: "src=R10,src2=R30,dst=R10", inst: SUB, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xcb}},
549 {name: "src=R10,src2=R30,dst=R30", inst: SUB, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xcb}},
550 {name: "src=R30,src2=RZR,dst=RZR", inst: SUB, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xcb}},
551 {name: "src=R30,src2=RZR,dst=R10", inst: SUB, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xcb}},
552 {name: "src=R30,src2=RZR,dst=R30", inst: SUB, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xcb}},
553 {name: "src=R30,src2=R10,dst=RZR", inst: SUB, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xcb}},
554 {name: "src=R30,src2=R10,dst=R10", inst: SUB, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xcb}},
555 {name: "src=R30,src2=R10,dst=R30", inst: SUB, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xcb}},
556 {name: "src=R30,src2=R30,dst=RZR", inst: SUB, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xcb}},
557 {name: "src=R30,src2=R30,dst=R10", inst: SUB, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xcb}},
558 {name: "src=R30,src2=R30,dst=R30", inst: SUB, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xcb}},
559 {name: "src=RZR,src2=RZR,dst=RZR", inst: SUBW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x4b}},
560 {name: "src=RZR,src2=RZR,dst=R10", inst: SUBW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x4b}},
561 {name: "src=RZR,src2=RZR,dst=R30", inst: SUBW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x4b}},
562 {name: "src=RZR,src2=R10,dst=RZR", inst: SUBW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x4b}},
563 {name: "src=RZR,src2=R10,dst=R10", inst: SUBW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x4b}},
564 {name: "src=RZR,src2=R10,dst=R30", inst: SUBW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x4b}},
565 {name: "src=RZR,src2=R30,dst=RZR", inst: SUBW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x4b}},
566 {name: "src=RZR,src2=R30,dst=R10", inst: SUBW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x4b}},
567 {name: "src=RZR,src2=R30,dst=R30", inst: SUBW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x4b}},
568 {name: "src=R10,src2=RZR,dst=RZR", inst: SUBW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x4b}},
569 {name: "src=R10,src2=RZR,dst=R10", inst: SUBW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x4b}},
570 {name: "src=R10,src2=RZR,dst=R30", inst: SUBW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x4b}},
571 {name: "src=R10,src2=R10,dst=RZR", inst: SUBW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x4b}},
572 {name: "src=R10,src2=R10,dst=R10", inst: SUBW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x4b}},
573 {name: "src=R10,src2=R10,dst=R30", inst: SUBW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x4b}},
574 {name: "src=R10,src2=R30,dst=RZR", inst: SUBW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x4b}},
575 {name: "src=R10,src2=R30,dst=R10", inst: SUBW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x4b}},
576 {name: "src=R10,src2=R30,dst=R30", inst: SUBW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x4b}},
577 {name: "src=R30,src2=RZR,dst=RZR", inst: SUBW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x4b}},
578 {name: "src=R30,src2=RZR,dst=R10", inst: SUBW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x4b}},
579 {name: "src=R30,src2=RZR,dst=R30", inst: SUBW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x4b}},
580 {name: "src=R30,src2=R10,dst=RZR", inst: SUBW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x4b}},
581 {name: "src=R30,src2=R10,dst=R10", inst: SUBW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x4b}},
582 {name: "src=R30,src2=R10,dst=R30", inst: SUBW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x4b}},
583 {name: "src=R30,src2=R30,dst=RZR", inst: SUBW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x4b}},
584 {name: "src=R30,src2=R30,dst=R10", inst: SUBW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x4b}},
585 {name: "src=R30,src2=R30,dst=R30", inst: SUBW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x4b}},
586 {name: "src=V0,src2=V0,dst=V0", inst: FSUBD, src: RegV0, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x60, 0x1e}},
587 {name: "src=V0,src2=V0,dst=V31", inst: FSUBD, src: RegV0, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x60, 0x1e}},
588 {name: "src=V0,src2=V31,dst=V0", inst: FSUBD, src: RegV0, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x60, 0x1e}},
589 {name: "src=V0,src2=V31,dst=V31", inst: FSUBD, src: RegV0, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x60, 0x1e}},
590 {name: "src=V31,src2=V0,dst=V0", inst: FSUBD, src: RegV31, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x7f, 0x1e}},
591 {name: "src=V31,src2=V0,dst=V31", inst: FSUBD, src: RegV31, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x7f, 0x1e}},
592 {name: "src=V31,src2=V31,dst=V0", inst: FSUBD, src: RegV31, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x7f, 0x1e}},
593 {name: "src=V31,src2=V31,dst=V31", inst: FSUBD, src: RegV31, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x7f, 0x1e}},
594 {name: "src=V0,src2=V0,dst=V0", inst: FSUBS, src: RegV0, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x20, 0x1e}},
595 {name: "src=V0,src2=V0,dst=V31", inst: FSUBS, src: RegV0, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x20, 0x1e}},
596 {name: "src=V0,src2=V31,dst=V0", inst: FSUBS, src: RegV0, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x20, 0x1e}},
597 {name: "src=V0,src2=V31,dst=V31", inst: FSUBS, src: RegV0, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x20, 0x1e}},
598 {name: "src=V31,src2=V0,dst=V0", inst: FSUBS, src: RegV31, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x3f, 0x1e}},
599 {name: "src=V31,src2=V0,dst=V31", inst: FSUBS, src: RegV31, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x3f, 0x1e}},
600 {name: "src=V31,src2=V31,dst=V0", inst: FSUBS, src: RegV31, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x3f, 0x1e}},
601 {name: "src=V31,src2=V31,dst=V31", inst: FSUBS, src: RegV31, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x3f, 0x1e}},
602 }
603
604 for _, tc := range tests {
605 t.Run(tc.name, func(t *testing.T) {
606 code := asm.CodeSegment{}
607 defer func() { require.NoError(t, code.Unmap()) }()
608
609 a := NewAssembler(asm.NilRegister)
610 buf := code.NextCodeSection()
611 err := a.encodeTwoRegistersToRegister(buf, &nodeImpl{instruction: tc.inst, srcReg: tc.src, srcReg2: tc.src2, dstReg: tc.dst})
612 require.NoError(t, err)
613
614 actual := buf.Bytes()
615 require.Equal(t, tc.exp, actual[:4])
616 })
617 }
618 }
619
620 func TestAssemblerImpl_EncodeRegisterAndConstToNone(t *testing.T) {
621 t.Run("error", func(t *testing.T) {
622 tests := []struct {
623 n *nodeImpl
624 expErr string
625 }{
626 {
627 n: &nodeImpl{
628 instruction: ADR, types: operandTypesRegisterAndConstToNone,
629 srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0,
630 },
631 expErr: "ADR is unsupported for RegisterAndConstToNone type",
632 },
633 {
634 n: &nodeImpl{
635 instruction: CMP, types: operandTypesRegisterAndConstToNone,
636 srcReg: RegR0, srcConst: 12345,
637 },
638 expErr: "immediate for CMP must fit in 0 to 4095 but got 12345",
639 },
640 {
641 n: &nodeImpl{
642 instruction: CMP, types: operandTypesRegisterAndConstToNone,
643 srcReg: RegRZR, srcConst: 123,
644 },
645 expErr: "zero register is not supported for CMP (immediate)",
646 },
647 }
648
649 code := asm.CodeSegment{}
650 defer func() { require.NoError(t, code.Unmap()) }()
651
652 for _, tt := range tests {
653 tc := tt
654 a := NewAssembler(asm.NilRegister)
655 buf := code.NextCodeSection()
656 err := a.encodeRegisterAndConstToNone(buf, tc.n)
657 require.EqualError(t, err, tc.expErr)
658 }
659 })
660
661 tests := []struct {
662 name string
663 exp []byte
664 c int64
665 inst asm.Instruction
666 reg asm.Register
667 }{
668 {name: "R1, 0", inst: CMP, reg: RegR1, c: 0, exp: []byte{0x3f, 0x0, 0x0, 0xf1}},
669 {name: "R1, 10", inst: CMP, reg: RegR1, c: 10, exp: []byte{0x3f, 0x28, 0x0, 0xf1}},
670 {name: "R1, 100", inst: CMP, reg: RegR1, c: 100, exp: []byte{0x3f, 0x90, 0x1, 0xf1}},
671 {name: "R1, 300", inst: CMP, reg: RegR1, c: 300, exp: []byte{0x3f, 0xb0, 0x4, 0xf1}},
672 {name: "R1, 4095", inst: CMP, reg: RegR1, c: 4095, exp: []byte{0x3f, 0xfc, 0x3f, 0xf1}},
673 {name: "R10, 0", inst: CMP, reg: RegR10, c: 0, exp: []byte{0x5f, 0x1, 0x0, 0xf1}},
674 {name: "R10, 10", inst: CMP, reg: RegR10, c: 10, exp: []byte{0x5f, 0x29, 0x0, 0xf1}},
675 {name: "R10, 100", inst: CMP, reg: RegR10, c: 100, exp: []byte{0x5f, 0x91, 0x1, 0xf1}},
676 {name: "R10, 300", inst: CMP, reg: RegR10, c: 300, exp: []byte{0x5f, 0xb1, 0x4, 0xf1}},
677 {name: "R10, 4095", inst: CMP, reg: RegR10, c: 4095, exp: []byte{0x5f, 0xfd, 0x3f, 0xf1}},
678 {name: "R30, 0", inst: CMP, reg: RegR30, c: 0, exp: []byte{0xdf, 0x3, 0x0, 0xf1}},
679 {name: "R30, 10", inst: CMP, reg: RegR30, c: 10, exp: []byte{0xdf, 0x2b, 0x0, 0xf1}},
680 {name: "R30, 100", inst: CMP, reg: RegR30, c: 100, exp: []byte{0xdf, 0x93, 0x1, 0xf1}},
681 {name: "R30, 300", inst: CMP, reg: RegR30, c: 300, exp: []byte{0xdf, 0xb3, 0x4, 0xf1}},
682 {name: "R30, 4095", inst: CMP, reg: RegR30, c: 4095, exp: []byte{0xdf, 0xff, 0x3f, 0xf1}},
683 }
684
685 for _, tc := range tests {
686 t.Run(tc.name, func(t *testing.T) {
687 code := asm.CodeSegment{}
688 defer func() { require.NoError(t, code.Unmap()) }()
689
690 a := NewAssembler(asm.NilRegister)
691 buf := code.NextCodeSection()
692 err := a.encodeRegisterAndConstToNone(buf, &nodeImpl{instruction: tc.inst, srcReg: tc.reg, srcConst: tc.c})
693 require.NoError(t, err)
694
695 actual := buf.Bytes()
696 require.Equal(t, tc.exp, actual[:4])
697 })
698 }
699 }
700
701 func TestAssemblerImpl_EncodeRegisterToRegister(t *testing.T) {
702 t.Run("error", func(t *testing.T) {
703 tests := []struct {
704 n *nodeImpl
705 expErr string
706 }{
707 {
708 n: &nodeImpl{
709 instruction: ADR, types: operandTypesRegisterToRegister,
710 srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0,
711 },
712 expErr: "ADR is unsupported for RegisterToRegister type",
713 },
714 }
715
716 code := asm.CodeSegment{}
717 defer func() { require.NoError(t, code.Unmap()) }()
718
719 for _, tt := range tests {
720 tc := tt
721 a := NewAssembler(asm.NilRegister)
722 buf := code.NextCodeSection()
723 err := a.encodeRegisterToRegister(buf, tc.n)
724 require.EqualError(t, err, tc.expErr)
725 }
726 })
727
728 tests := []struct {
729 name string
730 exp []byte
731 inst asm.Instruction
732 src asm.Register
733 dst asm.Register
734 }{
735 {name: "MOV/src=RegSP,dst=R10", inst: MOVD, src: RegSP, dst: RegR10, exp: []byte{0xea, 0x3, 0x0, 0x91}},
736 {name: "MOV/src=RegSP,dst=R30", inst: MOVD, src: RegSP, dst: RegR30, exp: []byte{0xfe, 0x3, 0x0, 0x91}},
737 {name: "MOV/src=R10,dst=RegSP", inst: MOVD, src: RegR10, dst: RegSP, exp: []byte{0x5f, 0x1, 0x0, 0x91}},
738 {name: "MOV/src=R10,dst=R10", inst: MOVD, src: RegR30, dst: RegSP, exp: []byte{0xdf, 0x3, 0x0, 0x91}},
739 {name: "MOV/src=R10,dst=RegSP", inst: MOVD, src: RegSP, dst: RegSP, exp: []byte{0xff, 0x3, 0x0, 0x91}},
740 {name: "ADD/src=RZR,dst=RZR", inst: ADD, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x8b}},
741 {name: "ADD/src=RZR,dst=R10", inst: ADD, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x8b}},
742 {name: "ADD/src=RZR,dst=R30", inst: ADD, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x8b}},
743 {name: "ADD/src=R10,dst=RZR", inst: ADD, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x8b}},
744 {name: "ADD/src=R10,dst=R10", inst: ADD, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x8b}},
745 {name: "ADD/src=R10,dst=R30", inst: ADD, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x8b}},
746 {name: "ADD/src=R30,dst=RZR", inst: ADD, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x8b}},
747 {name: "ADD/src=R30,dst=R10", inst: ADD, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x8b}},
748 {name: "ADD/src=R30,dst=R30", inst: ADD, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x8b}},
749 {name: "ADDW/src=RZR,dst=RZR", inst: ADDW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xb}},
750 {name: "ADDW/src=RZR,dst=R10", inst: ADDW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xb}},
751 {name: "ADDW/src=RZR,dst=R30", inst: ADDW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xb}},
752 {name: "ADDW/src=R10,dst=RZR", inst: ADDW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xb}},
753 {name: "ADDW/src=R10,dst=R10", inst: ADDW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xb}},
754 {name: "ADDW/src=R10,dst=R30", inst: ADDW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xb}},
755 {name: "ADDW/src=R30,dst=RZR", inst: ADDW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xb}},
756 {name: "ADDW/src=R30,dst=R10", inst: ADDW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xb}},
757 {name: "ADDW/src=R30,dst=R30", inst: ADDW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xb}},
758 {name: "SUB/src=RZR,dst=RZR", inst: SUB, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xcb}},
759 {name: "SUB/src=RZR,dst=R10", inst: SUB, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xcb}},
760 {name: "SUB/src=RZR,dst=R30", inst: SUB, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xcb}},
761 {name: "SUB/src=R10,dst=RZR", inst: SUB, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xcb}},
762 {name: "SUB/src=R10,dst=R10", inst: SUB, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xcb}},
763 {name: "SUB/src=R10,dst=R30", inst: SUB, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xcb}},
764 {name: "SUB/src=R30,dst=RZR", inst: SUB, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xcb}},
765 {name: "SUB/src=R30,dst=R10", inst: SUB, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xcb}},
766 {name: "SUB/src=R30,dst=R30", inst: SUB, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xcb}},
767 {name: "CLZ/src=RZR,dst=RZR", inst: CLZ, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xc0, 0xda}},
768 {name: "CLZ/src=RZR,dst=R10", inst: CLZ, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xc0, 0xda}},
769 {name: "CLZ/src=RZR,dst=R30", inst: CLZ, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xc0, 0xda}},
770 {name: "CLZ/src=R10,dst=RZR", inst: CLZ, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xc0, 0xda}},
771 {name: "CLZ/src=R10,dst=R10", inst: CLZ, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xc0, 0xda}},
772 {name: "CLZ/src=R10,dst=R30", inst: CLZ, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xc0, 0xda}},
773 {name: "CLZ/src=R30,dst=RZR", inst: CLZ, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xc0, 0xda}},
774 {name: "CLZ/src=R30,dst=R10", inst: CLZ, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xc0, 0xda}},
775 {name: "CLZ/src=R30,dst=R30", inst: CLZ, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xc0, 0xda}},
776 {name: "CLZW/src=RZR,dst=RZR", inst: CLZW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xc0, 0x5a}},
777 {name: "CLZW/src=RZR,dst=R10", inst: CLZW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xc0, 0x5a}},
778 {name: "CLZW/src=RZR,dst=R30", inst: CLZW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xc0, 0x5a}},
779 {name: "CLZW/src=R10,dst=RZR", inst: CLZW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xc0, 0x5a}},
780 {name: "CLZW/src=R10,dst=R10", inst: CLZW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xc0, 0x5a}},
781 {name: "CLZW/src=R10,dst=R30", inst: CLZW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xc0, 0x5a}},
782 {name: "CLZW/src=R30,dst=RZR", inst: CLZW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xc0, 0x5a}},
783 {name: "CLZW/src=R30,dst=R10", inst: CLZW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xc0, 0x5a}},
784 {name: "CLZW/src=R30,dst=R30", inst: CLZW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xc0, 0x5a}},
785 {name: "CSET/src=COND_EQ,dst=RZR", inst: CSET, src: RegCondEQ, dst: RegRZR, exp: []byte{0xff, 0x17, 0x9f, 0x9a}},
786 {name: "CSET/src=COND_EQ,dst=R10", inst: CSET, src: RegCondEQ, dst: RegR10, exp: []byte{0xea, 0x17, 0x9f, 0x9a}},
787 {name: "CSET/src=COND_EQ,dst=R30", inst: CSET, src: RegCondEQ, dst: RegR30, exp: []byte{0xfe, 0x17, 0x9f, 0x9a}},
788 {name: "CSET/src=COND_NE,dst=RZR", inst: CSET, src: RegCondNE, dst: RegRZR, exp: []byte{0xff, 0x7, 0x9f, 0x9a}},
789 {name: "CSET/src=COND_NE,dst=R10", inst: CSET, src: RegCondNE, dst: RegR10, exp: []byte{0xea, 0x7, 0x9f, 0x9a}},
790 {name: "CSET/src=COND_NE,dst=R30", inst: CSET, src: RegCondNE, dst: RegR30, exp: []byte{0xfe, 0x7, 0x9f, 0x9a}},
791 {name: "CSET/src=COND_HS,dst=RZR", inst: CSET, src: RegCondHS, dst: RegRZR, exp: []byte{0xff, 0x37, 0x9f, 0x9a}},
792 {name: "CSET/src=COND_HS,dst=R10", inst: CSET, src: RegCondHS, dst: RegR10, exp: []byte{0xea, 0x37, 0x9f, 0x9a}},
793 {name: "CSET/src=COND_HS,dst=R30", inst: CSET, src: RegCondHS, dst: RegR30, exp: []byte{0xfe, 0x37, 0x9f, 0x9a}},
794 {name: "CSET/src=COND_LO,dst=RZR", inst: CSET, src: RegCondLO, dst: RegRZR, exp: []byte{0xff, 0x27, 0x9f, 0x9a}},
795 {name: "CSET/src=COND_LO,dst=R10", inst: CSET, src: RegCondLO, dst: RegR10, exp: []byte{0xea, 0x27, 0x9f, 0x9a}},
796 {name: "CSET/src=COND_LO,dst=R30", inst: CSET, src: RegCondLO, dst: RegR30, exp: []byte{0xfe, 0x27, 0x9f, 0x9a}},
797 {name: "CSET/src=COND_MI,dst=RZR", inst: CSET, src: RegCondMI, dst: RegRZR, exp: []byte{0xff, 0x57, 0x9f, 0x9a}},
798 {name: "CSET/src=COND_MI,dst=R10", inst: CSET, src: RegCondMI, dst: RegR10, exp: []byte{0xea, 0x57, 0x9f, 0x9a}},
799 {name: "CSET/src=COND_MI,dst=R30", inst: CSET, src: RegCondMI, dst: RegR30, exp: []byte{0xfe, 0x57, 0x9f, 0x9a}},
800 {name: "CSET/src=COND_PL,dst=RZR", inst: CSET, src: RegCondPL, dst: RegRZR, exp: []byte{0xff, 0x47, 0x9f, 0x9a}},
801 {name: "CSET/src=COND_PL,dst=R10", inst: CSET, src: RegCondPL, dst: RegR10, exp: []byte{0xea, 0x47, 0x9f, 0x9a}},
802 {name: "CSET/src=COND_PL,dst=R30", inst: CSET, src: RegCondPL, dst: RegR30, exp: []byte{0xfe, 0x47, 0x9f, 0x9a}},
803 {name: "CSET/src=COND_VS,dst=RZR", inst: CSET, src: RegCondVS, dst: RegRZR, exp: []byte{0xff, 0x77, 0x9f, 0x9a}},
804 {name: "CSET/src=COND_VS,dst=R10", inst: CSET, src: RegCondVS, dst: RegR10, exp: []byte{0xea, 0x77, 0x9f, 0x9a}},
805 {name: "CSET/src=COND_VS,dst=R30", inst: CSET, src: RegCondVS, dst: RegR30, exp: []byte{0xfe, 0x77, 0x9f, 0x9a}},
806 {name: "CSET/src=COND_VC,dst=RZR", inst: CSET, src: RegCondVC, dst: RegRZR, exp: []byte{0xff, 0x67, 0x9f, 0x9a}},
807 {name: "CSET/src=COND_VC,dst=R10", inst: CSET, src: RegCondVC, dst: RegR10, exp: []byte{0xea, 0x67, 0x9f, 0x9a}},
808 {name: "CSET/src=COND_VC,dst=R30", inst: CSET, src: RegCondVC, dst: RegR30, exp: []byte{0xfe, 0x67, 0x9f, 0x9a}},
809 {name: "CSET/src=COND_HI,dst=RZR", inst: CSET, src: RegCondHI, dst: RegRZR, exp: []byte{0xff, 0x97, 0x9f, 0x9a}},
810 {name: "CSET/src=COND_HI,dst=R10", inst: CSET, src: RegCondHI, dst: RegR10, exp: []byte{0xea, 0x97, 0x9f, 0x9a}},
811 {name: "CSET/src=COND_HI,dst=R30", inst: CSET, src: RegCondHI, dst: RegR30, exp: []byte{0xfe, 0x97, 0x9f, 0x9a}},
812 {name: "CSET/src=COND_LS,dst=RZR", inst: CSET, src: RegCondLS, dst: RegRZR, exp: []byte{0xff, 0x87, 0x9f, 0x9a}},
813 {name: "CSET/src=COND_LS,dst=R10", inst: CSET, src: RegCondLS, dst: RegR10, exp: []byte{0xea, 0x87, 0x9f, 0x9a}},
814 {name: "CSET/src=COND_LS,dst=R30", inst: CSET, src: RegCondLS, dst: RegR30, exp: []byte{0xfe, 0x87, 0x9f, 0x9a}},
815 {name: "CSET/src=COND_GE,dst=RZR", inst: CSET, src: RegCondGE, dst: RegRZR, exp: []byte{0xff, 0xb7, 0x9f, 0x9a}},
816 {name: "CSET/src=COND_GE,dst=R10", inst: CSET, src: RegCondGE, dst: RegR10, exp: []byte{0xea, 0xb7, 0x9f, 0x9a}},
817 {name: "CSET/src=COND_GE,dst=R30", inst: CSET, src: RegCondGE, dst: RegR30, exp: []byte{0xfe, 0xb7, 0x9f, 0x9a}},
818 {name: "CSET/src=COND_LT,dst=RZR", inst: CSET, src: RegCondLT, dst: RegRZR, exp: []byte{0xff, 0xa7, 0x9f, 0x9a}},
819 {name: "CSET/src=COND_LT,dst=R10", inst: CSET, src: RegCondLT, dst: RegR10, exp: []byte{0xea, 0xa7, 0x9f, 0x9a}},
820 {name: "CSET/src=COND_LT,dst=R30", inst: CSET, src: RegCondLT, dst: RegR30, exp: []byte{0xfe, 0xa7, 0x9f, 0x9a}},
821 {name: "CSET/src=COND_GT,dst=RZR", inst: CSET, src: RegCondGT, dst: RegRZR, exp: []byte{0xff, 0xd7, 0x9f, 0x9a}},
822 {name: "CSET/src=COND_GT,dst=R10", inst: CSET, src: RegCondGT, dst: RegR10, exp: []byte{0xea, 0xd7, 0x9f, 0x9a}},
823 {name: "CSET/src=COND_GT,dst=R30", inst: CSET, src: RegCondGT, dst: RegR30, exp: []byte{0xfe, 0xd7, 0x9f, 0x9a}},
824 {name: "CSET/src=COND_LE,dst=RZR", inst: CSET, src: RegCondLE, dst: RegRZR, exp: []byte{0xff, 0xc7, 0x9f, 0x9a}},
825 {name: "CSET/src=COND_LE,dst=R10", inst: CSET, src: RegCondLE, dst: RegR10, exp: []byte{0xea, 0xc7, 0x9f, 0x9a}},
826 {name: "CSET/src=COND_LE,dst=R30", inst: CSET, src: RegCondLE, dst: RegR30, exp: []byte{0xfe, 0xc7, 0x9f, 0x9a}},
827 {name: "CSET/src=COND_AL,dst=RZR", inst: CSET, src: RegCondAL, dst: RegRZR, exp: []byte{0xff, 0xf7, 0x9f, 0x9a}},
828 {name: "CSET/src=COND_AL,dst=R10", inst: CSET, src: RegCondAL, dst: RegR10, exp: []byte{0xea, 0xf7, 0x9f, 0x9a}},
829 {name: "CSET/src=COND_AL,dst=R30", inst: CSET, src: RegCondAL, dst: RegR30, exp: []byte{0xfe, 0xf7, 0x9f, 0x9a}},
830 {name: "CSET/src=COND_NV,dst=RZR", inst: CSET, src: RegCondNV, dst: RegRZR, exp: []byte{0xff, 0xe7, 0x9f, 0x9a}},
831 {name: "CSET/src=COND_NV,dst=R10", inst: CSET, src: RegCondNV, dst: RegR10, exp: []byte{0xea, 0xe7, 0x9f, 0x9a}},
832 {name: "CSET/src=COND_NV,dst=R30", inst: CSET, src: RegCondNV, dst: RegR30, exp: []byte{0xfe, 0xe7, 0x9f, 0x9a}},
833 {name: "FABSS/src=V0,dst=V0", inst: FABSS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x20, 0x1e}},
834 {name: "FABSS/src=V0,dst=V31", inst: FABSS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x20, 0x1e}},
835 {name: "FABSS/src=V31,dst=V0", inst: FABSS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x20, 0x1e}},
836 {name: "FABSS/src=V31,dst=V31", inst: FABSS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x20, 0x1e}},
837 {name: "FABSD/src=V0,dst=V0", inst: FABSD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x60, 0x1e}},
838 {name: "FABSD/src=V0,dst=V31", inst: FABSD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x60, 0x1e}},
839 {name: "FABSD/src=V31,dst=V0", inst: FABSD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x60, 0x1e}},
840 {name: "FABSD/src=V31,dst=V31", inst: FABSD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x60, 0x1e}},
841 {name: "FNEGS/src=V0,dst=V0", inst: FNEGS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x21, 0x1e}},
842 {name: "FNEGS/src=V0,dst=V31", inst: FNEGS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x21, 0x1e}},
843 {name: "FNEGS/src=V31,dst=V0", inst: FNEGS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x21, 0x1e}},
844 {name: "FNEGS/src=V31,dst=V31", inst: FNEGS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x21, 0x1e}},
845 {name: "FNEGD/src=V0,dst=V0", inst: FNEGD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x61, 0x1e}},
846 {name: "FNEGD/src=V0,dst=V31", inst: FNEGD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x61, 0x1e}},
847 {name: "FNEGD/src=V31,dst=V0", inst: FNEGD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x61, 0x1e}},
848 {name: "FNEGD/src=V31,dst=V31", inst: FNEGD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x61, 0x1e}},
849 {name: "FSQRTD/src=V0,dst=V0", inst: FSQRTD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x61, 0x1e}},
850 {name: "FSQRTD/src=V0,dst=V31", inst: FSQRTD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x61, 0x1e}},
851 {name: "FSQRTD/src=V31,dst=V0", inst: FSQRTD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x61, 0x1e}},
852 {name: "FSQRTD/src=V31,dst=V31", inst: FSQRTD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x61, 0x1e}},
853 {name: "FSQRTS/src=V0,dst=V0", inst: FSQRTS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x21, 0x1e}},
854 {name: "FSQRTS/src=V0,dst=V31", inst: FSQRTS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x21, 0x1e}},
855 {name: "FSQRTS/src=V31,dst=V0", inst: FSQRTS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x21, 0x1e}},
856 {name: "FSQRTS/src=V31,dst=V31", inst: FSQRTS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x21, 0x1e}},
857 {name: "FCVTDS/src=V0,dst=V0", inst: FCVTDS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x62, 0x1e}},
858 {name: "FCVTDS/src=V0,dst=V31", inst: FCVTDS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x62, 0x1e}},
859 {name: "FCVTDS/src=V31,dst=V0", inst: FCVTDS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x62, 0x1e}},
860 {name: "FCVTDS/src=V31,dst=V31", inst: FCVTDS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x62, 0x1e}},
861 {name: "FCVTSD/src=V0,dst=V0", inst: FCVTSD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x22, 0x1e}},
862 {name: "FCVTSD/src=V0,dst=V31", inst: FCVTSD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x22, 0x1e}},
863 {name: "FCVTSD/src=V31,dst=V0", inst: FCVTSD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x22, 0x1e}},
864 {name: "FCVTSD/src=V31,dst=V31", inst: FCVTSD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x22, 0x1e}},
865 {name: "FRINTMD/src=V0,dst=V0", inst: FRINTMD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x65, 0x1e}},
866 {name: "FRINTMD/src=V0,dst=V31", inst: FRINTMD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x65, 0x1e}},
867 {name: "FRINTMD/src=V31,dst=V0", inst: FRINTMD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x65, 0x1e}},
868 {name: "FRINTMD/src=V31,dst=V31", inst: FRINTMD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x65, 0x1e}},
869 {name: "FRINTMS/src=V0,dst=V0", inst: FRINTMS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x25, 0x1e}},
870 {name: "FRINTMS/src=V0,dst=V31", inst: FRINTMS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x25, 0x1e}},
871 {name: "FRINTMS/src=V31,dst=V0", inst: FRINTMS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x25, 0x1e}},
872 {name: "FRINTMS/src=V31,dst=V31", inst: FRINTMS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x25, 0x1e}},
873 {name: "FRINTND/src=V0,dst=V0", inst: FRINTND, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x64, 0x1e}},
874 {name: "FRINTND/src=V0,dst=V31", inst: FRINTND, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x64, 0x1e}},
875 {name: "FRINTND/src=V31,dst=V0", inst: FRINTND, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x64, 0x1e}},
876 {name: "FRINTND/src=V31,dst=V31", inst: FRINTND, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x64, 0x1e}},
877 {name: "FRINTNS/src=V0,dst=V0", inst: FRINTNS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x24, 0x1e}},
878 {name: "FRINTNS/src=V0,dst=V31", inst: FRINTNS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x24, 0x1e}},
879 {name: "FRINTNS/src=V31,dst=V0", inst: FRINTNS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x24, 0x1e}},
880 {name: "FRINTNS/src=V31,dst=V31", inst: FRINTNS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x24, 0x1e}},
881 {name: "FRINTPD/src=V0,dst=V0", inst: FRINTPD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x64, 0x1e}},
882 {name: "FRINTPD/src=V0,dst=V31", inst: FRINTPD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x64, 0x1e}},
883 {name: "FRINTPD/src=V31,dst=V0", inst: FRINTPD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x64, 0x1e}},
884 {name: "FRINTPD/src=V31,dst=V31", inst: FRINTPD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x64, 0x1e}},
885 {name: "FRINTPS/src=V0,dst=V0", inst: FRINTPS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x24, 0x1e}},
886 {name: "FRINTPS/src=V0,dst=V31", inst: FRINTPS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x24, 0x1e}},
887 {name: "FRINTPS/src=V31,dst=V0", inst: FRINTPS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x24, 0x1e}},
888 {name: "FRINTPS/src=V31,dst=V31", inst: FRINTPS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x24, 0x1e}},
889 {name: "FRINTZD/src=V0,dst=V0", inst: FRINTZD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x65, 0x1e}},
890 {name: "FRINTZD/src=V0,dst=V31", inst: FRINTZD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x65, 0x1e}},
891 {name: "FRINTZD/src=V31,dst=V0", inst: FRINTZD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x65, 0x1e}},
892 {name: "FRINTZD/src=V31,dst=V31", inst: FRINTZD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x65, 0x1e}},
893 {name: "FRINTZS/src=V0,dst=V0", inst: FRINTZS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x25, 0x1e}},
894 {name: "FRINTZS/src=V0,dst=V31", inst: FRINTZS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x25, 0x1e}},
895 {name: "FRINTZS/src=V31,dst=V0", inst: FRINTZS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x25, 0x1e}},
896 {name: "FRINTZS/src=V31,dst=V31", inst: FRINTZS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x25, 0x1e}},
897 {name: "FDIVS/src=V0,dst=V0", inst: FDIVS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x18, 0x20, 0x1e}},
898 {name: "FDIVS/src=V0,dst=V31", inst: FDIVS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x1b, 0x20, 0x1e}},
899 {name: "FDIVS/src=V31,dst=V0", inst: FDIVS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x18, 0x3f, 0x1e}},
900 {name: "FDIVS/src=V31,dst=V31", inst: FDIVS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x1b, 0x3f, 0x1e}},
901 {name: "FDIVD/src=V0,dst=V0", inst: FDIVD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x18, 0x60, 0x1e}},
902 {name: "FDIVD/src=V0,dst=V31", inst: FDIVD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x1b, 0x60, 0x1e}},
903 {name: "FDIVD/src=V31,dst=V0", inst: FDIVD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x18, 0x7f, 0x1e}},
904 {name: "FDIVD/src=V31,dst=V31", inst: FDIVD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x1b, 0x7f, 0x1e}},
905 {name: "FMAXD/src=V0,dst=V0", inst: FMAXD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x48, 0x60, 0x1e}},
906 {name: "FMAXD/src=V0,dst=V31", inst: FMAXD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x4b, 0x60, 0x1e}},
907 {name: "FMAXD/src=V31,dst=V0", inst: FMAXD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x48, 0x7f, 0x1e}},
908 {name: "FMAXD/src=V31,dst=V31", inst: FMAXD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x4b, 0x7f, 0x1e}},
909 {name: "FMAXS/src=V0,dst=V0", inst: FMAXS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x48, 0x20, 0x1e}},
910 {name: "FMAXS/src=V0,dst=V31", inst: FMAXS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x4b, 0x20, 0x1e}},
911 {name: "FMAXS/src=V31,dst=V0", inst: FMAXS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x48, 0x3f, 0x1e}},
912 {name: "FMAXS/src=V31,dst=V31", inst: FMAXS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x4b, 0x3f, 0x1e}},
913 {name: "FMIND/src=V0,dst=V0", inst: FMIND, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x58, 0x60, 0x1e}},
914 {name: "FMIND/src=V0,dst=V31", inst: FMIND, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x5b, 0x60, 0x1e}},
915 {name: "FMIND/src=V31,dst=V0", inst: FMIND, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x58, 0x7f, 0x1e}},
916 {name: "FMIND/src=V31,dst=V31", inst: FMIND, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x5b, 0x7f, 0x1e}},
917 {name: "FMINS/src=V0,dst=V0", inst: FMINS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x58, 0x20, 0x1e}},
918 {name: "FMINS/src=V0,dst=V31", inst: FMINS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x5b, 0x20, 0x1e}},
919 {name: "FMINS/src=V31,dst=V0", inst: FMINS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x58, 0x3f, 0x1e}},
920 {name: "FMINS/src=V31,dst=V31", inst: FMINS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x5b, 0x3f, 0x1e}},
921 {name: "FMULS/src=V0,dst=V0", inst: FMULS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x8, 0x20, 0x1e}},
922 {name: "FMULS/src=V0,dst=V31", inst: FMULS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0xb, 0x20, 0x1e}},
923 {name: "FMULS/src=V31,dst=V0", inst: FMULS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x8, 0x3f, 0x1e}},
924 {name: "FMULS/src=V31,dst=V31", inst: FMULS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xb, 0x3f, 0x1e}},
925 {name: "FMULD/src=V0,dst=V0", inst: FMULD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x8, 0x60, 0x1e}},
926 {name: "FMULD/src=V0,dst=V31", inst: FMULD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0xb, 0x60, 0x1e}},
927 {name: "FMULD/src=V31,dst=V0", inst: FMULD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x8, 0x7f, 0x1e}},
928 {name: "FMULD/src=V31,dst=V31", inst: FMULD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xb, 0x7f, 0x1e}},
929 {name: "FADDD/src=V0,dst=V0", inst: FADDD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x28, 0x60, 0x1e}},
930 {name: "FADDD/src=V0,dst=V31", inst: FADDD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x2b, 0x60, 0x1e}},
931 {name: "FADDD/src=V31,dst=V0", inst: FADDD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x28, 0x7f, 0x1e}},
932 {name: "FADDD/src=V31,dst=V31", inst: FADDD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x2b, 0x7f, 0x1e}},
933 {name: "FADDS/src=V0,dst=V0", inst: FADDS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x28, 0x20, 0x1e}},
934 {name: "FADDS/src=V0,dst=V31", inst: FADDS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x2b, 0x20, 0x1e}},
935 {name: "FADDS/src=V31,dst=V0", inst: FADDS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x28, 0x3f, 0x1e}},
936 {name: "FADDS/src=V31,dst=V31", inst: FADDS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x2b, 0x3f, 0x1e}},
937 {name: "FCVTZSD/src=V0,dst=RZR", inst: FCVTZSD, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x78, 0x9e}},
938 {name: "FCVTZSD/src=V0,dst=R10", inst: FCVTZSD, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x78, 0x9e}},
939 {name: "FCVTZSD/src=V0,dst=R30", inst: FCVTZSD, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x78, 0x9e}},
940 {name: "FCVTZSD/src=V31,dst=RZR", inst: FCVTZSD, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x78, 0x9e}},
941 {name: "FCVTZSD/src=V31,dst=R10", inst: FCVTZSD, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x78, 0x9e}},
942 {name: "FCVTZSD/src=V31,dst=R30", inst: FCVTZSD, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x78, 0x9e}},
943 {name: "FCVTZSDW/src=V0,dst=RZR", inst: FCVTZSDW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x78, 0x1e}},
944 {name: "FCVTZSDW/src=V0,dst=R10", inst: FCVTZSDW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x78, 0x1e}},
945 {name: "FCVTZSDW/src=V0,dst=R30", inst: FCVTZSDW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x78, 0x1e}},
946 {name: "FCVTZSDW/src=V31,dst=RZR", inst: FCVTZSDW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x78, 0x1e}},
947 {name: "FCVTZSDW/src=V31,dst=R10", inst: FCVTZSDW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x78, 0x1e}},
948 {name: "FCVTZSDW/src=V31,dst=R30", inst: FCVTZSDW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x78, 0x1e}},
949 {name: "FCVTZSS/src=V0,dst=RZR", inst: FCVTZSS, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x38, 0x9e}},
950 {name: "FCVTZSS/src=V0,dst=R10", inst: FCVTZSS, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x38, 0x9e}},
951 {name: "FCVTZSS/src=V0,dst=R30", inst: FCVTZSS, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x38, 0x9e}},
952 {name: "FCVTZSS/src=V31,dst=RZR", inst: FCVTZSS, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x38, 0x9e}},
953 {name: "FCVTZSS/src=V31,dst=R10", inst: FCVTZSS, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x38, 0x9e}},
954 {name: "FCVTZSS/src=V31,dst=R30", inst: FCVTZSS, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x38, 0x9e}},
955 {name: "FCVTZSSW/src=V0,dst=RZR", inst: FCVTZSSW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x38, 0x1e}},
956 {name: "FCVTZSSW/src=V0,dst=R10", inst: FCVTZSSW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x38, 0x1e}},
957 {name: "FCVTZSSW/src=V0,dst=R30", inst: FCVTZSSW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x38, 0x1e}},
958 {name: "FCVTZSSW/src=V31,dst=RZR", inst: FCVTZSSW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x38, 0x1e}},
959 {name: "FCVTZSSW/src=V31,dst=R10", inst: FCVTZSSW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x38, 0x1e}},
960 {name: "FCVTZSSW/src=V31,dst=R30", inst: FCVTZSSW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x38, 0x1e}},
961 {name: "FCVTZUD/src=V0,dst=RZR", inst: FCVTZUD, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x79, 0x9e}},
962 {name: "FCVTZUD/src=V0,dst=R10", inst: FCVTZUD, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x79, 0x9e}},
963 {name: "FCVTZUD/src=V0,dst=R30", inst: FCVTZUD, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x79, 0x9e}},
964 {name: "FCVTZUD/src=V31,dst=RZR", inst: FCVTZUD, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x79, 0x9e}},
965 {name: "FCVTZUD/src=V31,dst=R10", inst: FCVTZUD, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x79, 0x9e}},
966 {name: "FCVTZUD/src=V31,dst=R30", inst: FCVTZUD, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x79, 0x9e}},
967 {name: "FCVTZUDW/src=V0,dst=RZR", inst: FCVTZUDW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x79, 0x1e}},
968 {name: "FCVTZUDW/src=V0,dst=R10", inst: FCVTZUDW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x79, 0x1e}},
969 {name: "FCVTZUDW/src=V0,dst=R30", inst: FCVTZUDW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x79, 0x1e}},
970 {name: "FCVTZUDW/src=V31,dst=RZR", inst: FCVTZUDW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x79, 0x1e}},
971 {name: "FCVTZUDW/src=V31,dst=R10", inst: FCVTZUDW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x79, 0x1e}},
972 {name: "FCVTZUDW/src=V31,dst=R30", inst: FCVTZUDW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x79, 0x1e}},
973 {name: "FCVTZUS/src=V0,dst=RZR", inst: FCVTZUS, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x39, 0x9e}},
974 {name: "FCVTZUS/src=V0,dst=R10", inst: FCVTZUS, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x39, 0x9e}},
975 {name: "FCVTZUS/src=V0,dst=R30", inst: FCVTZUS, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x39, 0x9e}},
976 {name: "FCVTZUS/src=V31,dst=RZR", inst: FCVTZUS, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x39, 0x9e}},
977 {name: "FCVTZUS/src=V31,dst=R10", inst: FCVTZUS, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x39, 0x9e}},
978 {name: "FCVTZUS/src=V31,dst=R30", inst: FCVTZUS, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x39, 0x9e}},
979 {name: "FCVTZUSW/src=V0,dst=RZR", inst: FCVTZUSW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x39, 0x1e}},
980 {name: "FCVTZUSW/src=V0,dst=R10", inst: FCVTZUSW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x39, 0x1e}},
981 {name: "FCVTZUSW/src=V0,dst=R30", inst: FCVTZUSW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x39, 0x1e}},
982 {name: "FCVTZUSW/src=V31,dst=RZR", inst: FCVTZUSW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x39, 0x1e}},
983 {name: "FCVTZUSW/src=V31,dst=R10", inst: FCVTZUSW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x39, 0x1e}},
984 {name: "FCVTZUSW/src=V31,dst=R30", inst: FCVTZUSW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x39, 0x1e}},
985 {name: "FMOVD/src=V0,dst=V0", inst: FMOVD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x60, 0x1e}},
986 {name: "FMOVD/src=V0,dst=V31", inst: FMOVD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x60, 0x1e}},
987 {name: "FMOVD/src=V31,dst=V0", inst: FMOVD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x60, 0x1e}},
988 {name: "FMOVD/src=V31,dst=V31", inst: FMOVD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x60, 0x1e}},
989 {name: "FMOVS/src=V0,dst=V0", inst: FMOVS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x20, 0x1e}},
990 {name: "FMOVS/src=V0,dst=V31", inst: FMOVS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x20, 0x1e}},
991 {name: "FMOVS/src=V31,dst=V0", inst: FMOVS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x20, 0x1e}},
992 {name: "FMOVS/src=V31,dst=V31", inst: FMOVS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x20, 0x1e}},
993 {name: "FMOVD/src=RZR,dst=V0", inst: FMOVD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x67, 0x9e}},
994 {name: "FMOVD/src=RZR,dst=V31", inst: FMOVD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x67, 0x9e}},
995 {name: "FMOVD/src=R10,dst=V0", inst: FMOVD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x67, 0x9e}},
996 {name: "FMOVD/src=R10,dst=V31", inst: FMOVD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x67, 0x9e}},
997 {name: "FMOVD/src=R30,dst=V0", inst: FMOVD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x67, 0x9e}},
998 {name: "FMOVD/src=R30,dst=V31", inst: FMOVD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x67, 0x9e}},
999 {name: "FMOVS/src=RZR,dst=V0", inst: FMOVS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x27, 0x1e}},
1000 {name: "FMOVS/src=RZR,dst=V31", inst: FMOVS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x27, 0x1e}},
1001 {name: "FMOVS/src=R10,dst=V0", inst: FMOVS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x27, 0x1e}},
1002 {name: "FMOVS/src=R10,dst=V31", inst: FMOVS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x27, 0x1e}},
1003 {name: "FMOVS/src=R30,dst=V0", inst: FMOVS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x27, 0x1e}},
1004 {name: "FMOVS/src=R30,dst=V31", inst: FMOVS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x27, 0x1e}},
1005 {name: "FMOVD/src=V0,dst=RZR", inst: FMOVD, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x66, 0x9e}},
1006 {name: "FMOVD/src=V0,dst=R10", inst: FMOVD, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x66, 0x9e}},
1007 {name: "FMOVD/src=V0,dst=R30", inst: FMOVD, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x66, 0x9e}},
1008 {name: "FMOVD/src=V31,dst=RZR", inst: FMOVD, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x66, 0x9e}},
1009 {name: "FMOVD/src=V31,dst=R10", inst: FMOVD, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x66, 0x9e}},
1010 {name: "FMOVD/src=V31,dst=R30", inst: FMOVD, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x66, 0x9e}},
1011 {name: "FMOVS/src=V0,dst=RZR", inst: FMOVS, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x26, 0x1e}},
1012 {name: "FMOVS/src=V0,dst=R10", inst: FMOVS, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x26, 0x1e}},
1013 {name: "FMOVS/src=V0,dst=R30", inst: FMOVS, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x26, 0x1e}},
1014 {name: "FMOVS/src=V31,dst=RZR", inst: FMOVS, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x26, 0x1e}},
1015 {name: "FMOVS/src=V31,dst=R10", inst: FMOVS, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x26, 0x1e}},
1016 {name: "FMOVS/src=V31,dst=R30", inst: FMOVS, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x26, 0x1e}},
1017 {name: "MOVD/src=RZR,dst=R10", inst: MOVD, src: RegRZR, dst: RegR10, exp: []byte{0xa, 0x0, 0x80, 0xd2}},
1018 {name: "MOVD/src=RZR,dst=R30", inst: MOVD, src: RegRZR, dst: RegR30, exp: []byte{0x1e, 0x0, 0x80, 0xd2}},
1019 {name: "MOVD/src=R10,dst=R10", inst: MOVD, src: RegR10, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xaa}},
1020 {name: "MOVD/src=R10,dst=R30", inst: MOVD, src: RegR10, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xaa}},
1021 {name: "MOVD/src=R30,dst=R10", inst: MOVD, src: RegR30, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xaa}},
1022 {name: "MOVD/src=R30,dst=R30", inst: MOVD, src: RegR30, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xaa}},
1023 {name: "MRS/src=FPSR,dst=RZR", inst: MRS, src: RegFPSR, dst: RegRZR, exp: []byte{0x3f, 0x44, 0x3b, 0xd5}},
1024 {name: "MRS/src=FPSR,dst=R10", inst: MRS, src: RegFPSR, dst: RegR10, exp: []byte{0x2a, 0x44, 0x3b, 0xd5}},
1025 {name: "MRS/src=FPSR,dst=R30", inst: MRS, src: RegFPSR, dst: RegR30, exp: []byte{0x3e, 0x44, 0x3b, 0xd5}},
1026 {name: "MSR/src=RZR,dst=FPSR", inst: MSR, src: RegRZR, dst: RegFPSR, exp: []byte{0x3f, 0x44, 0x1b, 0xd5}},
1027 {name: "MSR/src=R10,dst=FPSR", inst: MSR, src: RegR10, dst: RegFPSR, exp: []byte{0x2a, 0x44, 0x1b, 0xd5}},
1028 {name: "MSR/src=R30,dst=FPSR", inst: MSR, src: RegR30, dst: RegFPSR, exp: []byte{0x3e, 0x44, 0x1b, 0xd5}},
1029 {name: "MUL/src=RZR,dst=RZR", inst: MUL, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1f, 0x9b}},
1030 {name: "MUL/src=RZR,dst=R10", inst: MUL, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1f, 0x9b}},
1031 {name: "MUL/src=RZR,dst=R30", inst: MUL, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1f, 0x9b}},
1032 {name: "MUL/src=R10,dst=RZR", inst: MUL, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x7f, 0xa, 0x9b}},
1033 {name: "MUL/src=R10,dst=R10", inst: MUL, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x7d, 0xa, 0x9b}},
1034 {name: "MUL/src=R10,dst=R30", inst: MUL, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x7f, 0xa, 0x9b}},
1035 {name: "MUL/src=R30,dst=RZR", inst: MUL, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1e, 0x9b}},
1036 {name: "MUL/src=R30,dst=R10", inst: MUL, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1e, 0x9b}},
1037 {name: "MUL/src=R30,dst=R30", inst: MUL, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1e, 0x9b}},
1038 {name: "MULW/src=RZR,dst=RZR", inst: MULW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1f, 0x1b}},
1039 {name: "MULW/src=RZR,dst=R10", inst: MULW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1f, 0x1b}},
1040 {name: "MULW/src=RZR,dst=R30", inst: MULW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1f, 0x1b}},
1041 {name: "MULW/src=R10,dst=RZR", inst: MULW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x7f, 0xa, 0x1b}},
1042 {name: "MULW/src=R10,dst=R10", inst: MULW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x7d, 0xa, 0x1b}},
1043 {name: "MULW/src=R10,dst=R30", inst: MULW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x7f, 0xa, 0x1b}},
1044 {name: "MULW/src=R30,dst=RZR", inst: MULW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1e, 0x1b}},
1045 {name: "MULW/src=R30,dst=R10", inst: MULW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1e, 0x1b}},
1046 {name: "MULW/src=R30,dst=R30", inst: MULW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1e, 0x1b}},
1047 {name: "NEG/src=RZR,dst=RZR", inst: NEG, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xcb}},
1048 {name: "NEG/src=RZR,dst=R10", inst: NEG, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xcb}},
1049 {name: "NEG/src=RZR,dst=R30", inst: NEG, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xcb}},
1050 {name: "NEG/src=R10,dst=RZR", inst: NEG, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xcb}},
1051 {name: "NEG/src=R10,dst=R10", inst: NEG, src: RegR10, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xcb}},
1052 {name: "NEG/src=R10,dst=R30", inst: NEG, src: RegR10, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xcb}},
1053 {name: "NEG/src=R30,dst=RZR", inst: NEG, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xcb}},
1054 {name: "NEG/src=R30,dst=R10", inst: NEG, src: RegR30, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xcb}},
1055 {name: "NEG/src=R30,dst=R30", inst: NEG, src: RegR30, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xcb}},
1056 {name: "NEGW/src=RZR,dst=RZR", inst: NEGW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x4b}},
1057 {name: "NEGW/src=RZR,dst=R10", inst: NEGW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x4b}},
1058 {name: "NEGW/src=RZR,dst=R30", inst: NEGW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x4b}},
1059 {name: "NEGW/src=R10,dst=RZR", inst: NEGW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x4b}},
1060 {name: "NEGW/src=R10,dst=R10", inst: NEGW, src: RegR10, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x4b}},
1061 {name: "NEGW/src=R10,dst=R30", inst: NEGW, src: RegR10, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x4b}},
1062 {name: "NEGW/src=R30,dst=RZR", inst: NEGW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x4b}},
1063 {name: "NEGW/src=R30,dst=R10", inst: NEGW, src: RegR30, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x4b}},
1064 {name: "NEGW/src=R30,dst=R30", inst: NEGW, src: RegR30, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x4b}},
1065 {name: "RBIT/src=RZR,dst=RZR", inst: RBIT, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xc0, 0xda}},
1066 {name: "RBIT/src=RZR,dst=R10", inst: RBIT, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xc0, 0xda}},
1067 {name: "RBIT/src=RZR,dst=R30", inst: RBIT, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xc0, 0xda}},
1068 {name: "RBIT/src=R10,dst=RZR", inst: RBIT, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xc0, 0xda}},
1069 {name: "RBIT/src=R10,dst=R10", inst: RBIT, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xc0, 0xda}},
1070 {name: "RBIT/src=R10,dst=R30", inst: RBIT, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xc0, 0xda}},
1071 {name: "RBIT/src=R30,dst=RZR", inst: RBIT, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xc0, 0xda}},
1072 {name: "RBIT/src=R30,dst=R10", inst: RBIT, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xc0, 0xda}},
1073 {name: "RBIT/src=R30,dst=R30", inst: RBIT, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xc0, 0xda}},
1074 {name: "RBITW/src=RZR,dst=RZR", inst: RBITW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xc0, 0x5a}},
1075 {name: "RBITW/src=RZR,dst=R10", inst: RBITW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xc0, 0x5a}},
1076 {name: "RBITW/src=RZR,dst=R30", inst: RBITW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xc0, 0x5a}},
1077 {name: "RBITW/src=R10,dst=RZR", inst: RBITW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xc0, 0x5a}},
1078 {name: "RBITW/src=R10,dst=R10", inst: RBITW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xc0, 0x5a}},
1079 {name: "RBITW/src=R10,dst=R30", inst: RBITW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xc0, 0x5a}},
1080 {name: "RBITW/src=R30,dst=RZR", inst: RBITW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xc0, 0x5a}},
1081 {name: "RBITW/src=R30,dst=R10", inst: RBITW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xc0, 0x5a}},
1082 {name: "RBITW/src=R30,dst=R30", inst: RBITW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xc0, 0x5a}},
1083 {name: "SDIV/src=RZR,dst=RZR", inst: SDIV, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x9a}},
1084 {name: "SDIV/src=RZR,dst=R10", inst: SDIV, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x9a}},
1085 {name: "SDIV/src=RZR,dst=R30", inst: SDIV, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x9a}},
1086 {name: "SDIV/src=R10,dst=RZR", inst: SDIV, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x9a}},
1087 {name: "SDIV/src=R10,dst=R10", inst: SDIV, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x9a}},
1088 {name: "SDIV/src=R10,dst=R30", inst: SDIV, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x9a}},
1089 {name: "SDIV/src=R30,dst=RZR", inst: SDIV, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x9a}},
1090 {name: "SDIV/src=R30,dst=R10", inst: SDIV, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x9a}},
1091 {name: "SDIV/src=R30,dst=R30", inst: SDIV, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x9a}},
1092 {name: "SDIVW/src=RZR,dst=RZR", inst: SDIVW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x1a}},
1093 {name: "SDIVW/src=RZR,dst=R10", inst: SDIVW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x1a}},
1094 {name: "SDIVW/src=RZR,dst=R30", inst: SDIVW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x1a}},
1095 {name: "SDIVW/src=R10,dst=RZR", inst: SDIVW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x1a}},
1096 {name: "SDIVW/src=R10,dst=R10", inst: SDIVW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x1a}},
1097 {name: "SDIVW/src=R10,dst=R30", inst: SDIVW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x1a}},
1098 {name: "SDIVW/src=R30,dst=RZR", inst: SDIVW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x1a}},
1099 {name: "SDIVW/src=R30,dst=R10", inst: SDIVW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x1a}},
1100 {name: "SDIVW/src=R30,dst=R30", inst: SDIVW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x1a}},
1101 {name: "UDIV/src=RZR,dst=RZR", inst: UDIV, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x9a}},
1102 {name: "UDIV/src=RZR,dst=R10", inst: UDIV, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x9a}},
1103 {name: "UDIV/src=RZR,dst=R30", inst: UDIV, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x9a}},
1104 {name: "UDIV/src=R10,dst=RZR", inst: UDIV, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x9a}},
1105 {name: "UDIV/src=R10,dst=R10", inst: UDIV, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x9a}},
1106 {name: "UDIV/src=R10,dst=R30", inst: UDIV, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x9a}},
1107 {name: "UDIV/src=R30,dst=RZR", inst: UDIV, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x9a}},
1108 {name: "UDIV/src=R30,dst=R10", inst: UDIV, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x9a}},
1109 {name: "UDIV/src=R30,dst=R30", inst: UDIV, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x9a}},
1110 {name: "UDIVW/src=RZR,dst=RZR", inst: UDIVW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x1a}},
1111 {name: "UDIVW/src=RZR,dst=R10", inst: UDIVW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x1a}},
1112 {name: "UDIVW/src=RZR,dst=R30", inst: UDIVW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x1a}},
1113 {name: "UDIVW/src=R10,dst=RZR", inst: UDIVW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x1a}},
1114 {name: "UDIVW/src=R10,dst=R10", inst: UDIVW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x1a}},
1115 {name: "UDIVW/src=R10,dst=R30", inst: UDIVW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x1a}},
1116 {name: "UDIVW/src=R30,dst=RZR", inst: UDIVW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x1a}},
1117 {name: "UDIVW/src=R30,dst=R10", inst: UDIVW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x1a}},
1118 {name: "UDIVW/src=R30,dst=R30", inst: UDIVW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x1a}},
1119 {name: "SCVTFD/src=RZR,dst=V0", inst: SCVTFD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x62, 0x9e}},
1120 {name: "SCVTFD/src=RZR,dst=V31", inst: SCVTFD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x62, 0x9e}},
1121 {name: "SCVTFD/src=R10,dst=V0", inst: SCVTFD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x62, 0x9e}},
1122 {name: "SCVTFD/src=R10,dst=V31", inst: SCVTFD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x62, 0x9e}},
1123 {name: "SCVTFD/src=R30,dst=V0", inst: SCVTFD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x62, 0x9e}},
1124 {name: "SCVTFD/src=R30,dst=V31", inst: SCVTFD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x62, 0x9e}},
1125 {name: "SCVTFWD/src=RZR,dst=V0", inst: SCVTFWD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x62, 0x1e}},
1126 {name: "SCVTFWD/src=RZR,dst=V31", inst: SCVTFWD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x62, 0x1e}},
1127 {name: "SCVTFWD/src=R10,dst=V0", inst: SCVTFWD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x62, 0x1e}},
1128 {name: "SCVTFWD/src=R10,dst=V31", inst: SCVTFWD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x62, 0x1e}},
1129 {name: "SCVTFWD/src=R30,dst=V0", inst: SCVTFWD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x62, 0x1e}},
1130 {name: "SCVTFWD/src=R30,dst=V31", inst: SCVTFWD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x62, 0x1e}},
1131 {name: "SCVTFS/src=RZR,dst=V0", inst: SCVTFS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x22, 0x9e}},
1132 {name: "SCVTFS/src=RZR,dst=V31", inst: SCVTFS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x22, 0x9e}},
1133 {name: "SCVTFS/src=R10,dst=V0", inst: SCVTFS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x22, 0x9e}},
1134 {name: "SCVTFS/src=R10,dst=V31", inst: SCVTFS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x22, 0x9e}},
1135 {name: "SCVTFS/src=R30,dst=V0", inst: SCVTFS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x22, 0x9e}},
1136 {name: "SCVTFS/src=R30,dst=V31", inst: SCVTFS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x22, 0x9e}},
1137 {name: "SCVTFWS/src=RZR,dst=V0", inst: SCVTFWS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x22, 0x1e}},
1138 {name: "SCVTFWS/src=RZR,dst=V31", inst: SCVTFWS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x22, 0x1e}},
1139 {name: "SCVTFWS/src=R10,dst=V0", inst: SCVTFWS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x22, 0x1e}},
1140 {name: "SCVTFWS/src=R10,dst=V31", inst: SCVTFWS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x22, 0x1e}},
1141 {name: "SCVTFWS/src=R30,dst=V0", inst: SCVTFWS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x22, 0x1e}},
1142 {name: "SCVTFWS/src=R30,dst=V31", inst: SCVTFWS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x22, 0x1e}},
1143 {name: "UCVTFD/src=RZR,dst=V0", inst: UCVTFD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x63, 0x9e}},
1144 {name: "UCVTFD/src=RZR,dst=V31", inst: UCVTFD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x63, 0x9e}},
1145 {name: "UCVTFD/src=R10,dst=V0", inst: UCVTFD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x63, 0x9e}},
1146 {name: "UCVTFD/src=R10,dst=V31", inst: UCVTFD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x63, 0x9e}},
1147 {name: "UCVTFD/src=R30,dst=V0", inst: UCVTFD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x63, 0x9e}},
1148 {name: "UCVTFD/src=R30,dst=V31", inst: UCVTFD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x63, 0x9e}},
1149 {name: "UCVTFWD/src=RZR,dst=V0", inst: UCVTFWD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x63, 0x1e}},
1150 {name: "UCVTFWD/src=RZR,dst=V31", inst: UCVTFWD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x63, 0x1e}},
1151 {name: "UCVTFWD/src=R10,dst=V0", inst: UCVTFWD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x63, 0x1e}},
1152 {name: "UCVTFWD/src=R10,dst=V31", inst: UCVTFWD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x63, 0x1e}},
1153 {name: "UCVTFWD/src=R30,dst=V0", inst: UCVTFWD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x63, 0x1e}},
1154 {name: "UCVTFWD/src=R30,dst=V31", inst: UCVTFWD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x63, 0x1e}},
1155 {name: "UCVTFS/src=RZR,dst=V0", inst: UCVTFS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x23, 0x9e}},
1156 {name: "UCVTFS/src=RZR,dst=V31", inst: UCVTFS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x23, 0x9e}},
1157 {name: "UCVTFS/src=R10,dst=V0", inst: UCVTFS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x23, 0x9e}},
1158 {name: "UCVTFS/src=R10,dst=V31", inst: UCVTFS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x23, 0x9e}},
1159 {name: "UCVTFS/src=R30,dst=V0", inst: UCVTFS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x23, 0x9e}},
1160 {name: "UCVTFS/src=R30,dst=V31", inst: UCVTFS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x23, 0x9e}},
1161 {name: "UCVTFWS/src=RZR,dst=V0", inst: UCVTFWS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x23, 0x1e}},
1162 {name: "UCVTFWS/src=RZR,dst=V31", inst: UCVTFWS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x23, 0x1e}},
1163 {name: "UCVTFWS/src=R10,dst=V0", inst: UCVTFWS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x23, 0x1e}},
1164 {name: "UCVTFWS/src=R10,dst=V31", inst: UCVTFWS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x23, 0x1e}},
1165 {name: "UCVTFWS/src=R30,dst=V0", inst: UCVTFWS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x23, 0x1e}},
1166 {name: "UCVTFWS/src=R30,dst=V31", inst: UCVTFWS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x23, 0x1e}},
1167 {name: "SXTB/src=RZR,dst=RZR", inst: SXTB, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
1168 {name: "SXTB/src=RZR,dst=R10", inst: SXTB, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
1169 {name: "SXTB/src=RZR,dst=R30", inst: SXTB, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
1170 {name: "SXTB/src=R10,dst=RZR", inst: SXTB, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1d, 0x40, 0x93}},
1171 {name: "SXTB/src=R10,dst=R10", inst: SXTB, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1d, 0x40, 0x93}},
1172 {name: "SXTB/src=R10,dst=R30", inst: SXTB, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1d, 0x40, 0x93}},
1173 {name: "SXTB/src=R30,dst=RZR", inst: SXTB, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x1f, 0x40, 0x93}},
1174 {name: "SXTB/src=R30,dst=R10", inst: SXTB, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x1f, 0x40, 0x93}},
1175 {name: "SXTB/src=R30,dst=R30", inst: SXTB, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x1f, 0x40, 0x93}},
1176 {name: "SXTBW/src=RZR,dst=RZR", inst: SXTBW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
1177 {name: "SXTBW/src=RZR,dst=R10", inst: SXTBW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
1178 {name: "SXTBW/src=RZR,dst=R30", inst: SXTBW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
1179 {name: "SXTBW/src=R10,dst=RZR", inst: SXTBW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1d, 0x0, 0x13}},
1180 {name: "SXTBW/src=R10,dst=R10", inst: SXTBW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1d, 0x0, 0x13}},
1181 {name: "SXTBW/src=R10,dst=R30", inst: SXTBW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1d, 0x0, 0x13}},
1182 {name: "SXTBW/src=R30,dst=RZR", inst: SXTBW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x1f, 0x0, 0x13}},
1183 {name: "SXTBW/src=R30,dst=R10", inst: SXTBW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x1f, 0x0, 0x13}},
1184 {name: "SXTBW/src=R30,dst=R30", inst: SXTBW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x1f, 0x0, 0x13}},
1185 {name: "SXTH/src=RZR,dst=RZR", inst: SXTH, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
1186 {name: "SXTH/src=RZR,dst=R10", inst: SXTH, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
1187 {name: "SXTH/src=RZR,dst=R30", inst: SXTH, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
1188 {name: "SXTH/src=R10,dst=RZR", inst: SXTH, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x3d, 0x40, 0x93}},
1189 {name: "SXTH/src=R10,dst=R10", inst: SXTH, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x3d, 0x40, 0x93}},
1190 {name: "SXTH/src=R10,dst=R30", inst: SXTH, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x3d, 0x40, 0x93}},
1191 {name: "SXTH/src=R30,dst=RZR", inst: SXTH, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3f, 0x40, 0x93}},
1192 {name: "SXTH/src=R30,dst=R10", inst: SXTH, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3f, 0x40, 0x93}},
1193 {name: "SXTH/src=R30,dst=R30", inst: SXTH, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3f, 0x40, 0x93}},
1194 {name: "SXTHW/src=RZR,dst=RZR", inst: SXTHW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
1195 {name: "SXTHW/src=RZR,dst=R10", inst: SXTHW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
1196 {name: "SXTHW/src=RZR,dst=R30", inst: SXTHW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
1197 {name: "SXTHW/src=R10,dst=RZR", inst: SXTHW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x3d, 0x0, 0x13}},
1198 {name: "SXTHW/src=R10,dst=R10", inst: SXTHW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x3d, 0x0, 0x13}},
1199 {name: "SXTHW/src=R10,dst=R30", inst: SXTHW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x3d, 0x0, 0x13}},
1200 {name: "SXTHW/src=R30,dst=RZR", inst: SXTHW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3f, 0x0, 0x13}},
1201 {name: "SXTHW/src=R30,dst=R10", inst: SXTHW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3f, 0x0, 0x13}},
1202 {name: "SXTHW/src=R30,dst=R30", inst: SXTHW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3f, 0x0, 0x13}},
1203 {name: "SXTW/src=RZR,dst=RZR", inst: SXTW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
1204 {name: "SXTW/src=RZR,dst=R10", inst: SXTW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
1205 {name: "SXTW/src=RZR,dst=R30", inst: SXTW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
1206 {name: "SXTW/src=R10,dst=RZR", inst: SXTW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x7d, 0x40, 0x93}},
1207 {name: "SXTW/src=R10,dst=R10", inst: SXTW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x40, 0x93}},
1208 {name: "SXTW/src=R10,dst=R30", inst: SXTW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x7d, 0x40, 0x93}},
1209 {name: "SXTW/src=R30,dst=RZR", inst: SXTW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x7f, 0x40, 0x93}},
1210 {name: "SXTW/src=R30,dst=R10", inst: SXTW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x7f, 0x40, 0x93}},
1211 {name: "SXTW/src=R30,dst=R30", inst: SXTW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x7f, 0x40, 0x93}},
1212 }
1213
1214 for _, tc := range tests {
1215 t.Run(tc.name, func(t *testing.T) {
1216 code := asm.CodeSegment{}
1217 defer func() { require.NoError(t, code.Unmap()) }()
1218
1219 a := NewAssembler(asm.NilRegister)
1220 buf := code.NextCodeSection()
1221 err := a.encodeRegisterToRegister(buf, &nodeImpl{instruction: tc.inst, srcReg: tc.src, dstReg: tc.dst})
1222 require.NoError(t, err)
1223
1224 actual := buf.Bytes()
1225 require.Equal(t, tc.exp, actual[:4], hex.EncodeToString(actual[:4]))
1226 })
1227 }
1228 }
1229
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