1 package amd64
2
3 import (
4 "testing"
5
6 "github.com/tetratelabs/wazero/internal/asm"
7 "github.com/tetratelabs/wazero/internal/testing/require"
8 )
9
10 func TestAssemblerImpl_EncodeNoneToRegister(t *testing.T) {
11 t.Run("error", func(t *testing.T) {
12 code := asm.CodeSegment{}
13 defer func() { require.NoError(t, code.Unmap()) }()
14
15 a := NewAssembler()
16 buf := code.NextCodeSection()
17 err := a.encodeNoneToRegister(buf, &nodeImpl{
18 instruction: ADDL,
19 types: operandTypesNoneToRegister, dstReg: RegAX,
20 })
21 require.Error(t, err)
22
23 t.Run("error", func(t *testing.T) {
24 tests := []struct {
25 n *nodeImpl
26 expErr string
27 }{
28 {
29 n: &nodeImpl{instruction: ADDL, types: operandTypesNoneToRegister, dstReg: RegAX},
30 expErr: "ADDL is unsupported for NoneToRegister type",
31 },
32 }
33
34 code := asm.CodeSegment{}
35 defer func() { require.NoError(t, code.Unmap()) }()
36
37 for _, tt := range tests {
38 a := NewAssembler()
39 buf := code.NextCodeSection()
40 err := a.encodeNoneToRegister(buf, tt.n)
41 require.EqualError(t, err, tt.expErr, tt.expErr)
42 }
43 })
44 })
45
46 tests := []struct {
47 name string
48 inst asm.Instruction
49 dst asm.Register
50 exp []byte
51 }{
52 {name: "inst=JMP/reg=AX", inst: JMP, dst: RegAX, exp: []byte{0xff, 0xe0}},
53 {name: "inst=JMP/reg=BX", inst: JMP, dst: RegBX, exp: []byte{0xff, 0xe3}},
54 {name: "inst=JMP/reg=SP", inst: JMP, dst: RegSP, exp: []byte{0xff, 0xe4}},
55 {name: "inst=JMP/reg=BP", inst: JMP, dst: RegBP, exp: []byte{0xff, 0xe5}},
56 {name: "inst=JMP/reg=SI", inst: JMP, dst: RegSI, exp: []byte{0xff, 0xe6}},
57 {name: "inst=JMP/reg=DI", inst: JMP, dst: RegDI, exp: []byte{0xff, 0xe7}},
58 {name: "inst=JMP/reg=R8", inst: JMP, dst: RegR8, exp: []byte{0x41, 0xff, 0xe0}},
59 {name: "inst=JMP/reg=R9", inst: JMP, dst: RegR9, exp: []byte{0x41, 0xff, 0xe1}},
60 {name: "inst=JMP/reg=R13", inst: JMP, dst: RegR13, exp: []byte{0x41, 0xff, 0xe5}},
61 {name: "inst=JMP/reg=R14", inst: JMP, dst: RegR14, exp: []byte{0x41, 0xff, 0xe6}},
62 {name: "inst=JMP/reg=R15", inst: JMP, dst: RegR15, exp: []byte{0x41, 0xff, 0xe7}},
63 {name: "inst=SETCC/reg=AX", inst: SETCC, dst: RegAX, exp: []byte{0xf, 0x93, 0xc0}},
64 {name: "inst=SETCC/reg=BX", inst: SETCC, dst: RegBX, exp: []byte{0xf, 0x93, 0xc3}},
65 {name: "inst=SETCC/reg=SP", inst: SETCC, dst: RegSP, exp: []byte{0x40, 0xf, 0x93, 0xc4}},
66 {name: "inst=SETCC/reg=BP", inst: SETCC, dst: RegBP, exp: []byte{0x40, 0xf, 0x93, 0xc5}},
67 {name: "inst=SETCC/reg=SI", inst: SETCC, dst: RegSI, exp: []byte{0x40, 0xf, 0x93, 0xc6}},
68 {name: "inst=SETCC/reg=DI", inst: SETCC, dst: RegDI, exp: []byte{0x40, 0xf, 0x93, 0xc7}},
69 {name: "inst=SETCC/reg=R8", inst: SETCC, dst: RegR8, exp: []byte{0x41, 0xf, 0x93, 0xc0}},
70 {name: "inst=SETCC/reg=R9", inst: SETCC, dst: RegR9, exp: []byte{0x41, 0xf, 0x93, 0xc1}},
71 {name: "inst=SETCC/reg=R13", inst: SETCC, dst: RegR13, exp: []byte{0x41, 0xf, 0x93, 0xc5}},
72 {name: "inst=SETCC/reg=R14", inst: SETCC, dst: RegR14, exp: []byte{0x41, 0xf, 0x93, 0xc6}},
73 {name: "inst=SETCC/reg=R15", inst: SETCC, dst: RegR15, exp: []byte{0x41, 0xf, 0x93, 0xc7}},
74 {name: "inst=SETCS/reg=AX", inst: SETCS, dst: RegAX, exp: []byte{0xf, 0x92, 0xc0}},
75 {name: "inst=SETCS/reg=BX", inst: SETCS, dst: RegBX, exp: []byte{0xf, 0x92, 0xc3}},
76 {name: "inst=SETCS/reg=SP", inst: SETCS, dst: RegSP, exp: []byte{0x40, 0xf, 0x92, 0xc4}},
77 {name: "inst=SETCS/reg=BP", inst: SETCS, dst: RegBP, exp: []byte{0x40, 0xf, 0x92, 0xc5}},
78 {name: "inst=SETCS/reg=SI", inst: SETCS, dst: RegSI, exp: []byte{0x40, 0xf, 0x92, 0xc6}},
79 {name: "inst=SETCS/reg=DI", inst: SETCS, dst: RegDI, exp: []byte{0x40, 0xf, 0x92, 0xc7}},
80 {name: "inst=SETCS/reg=R8", inst: SETCS, dst: RegR8, exp: []byte{0x41, 0xf, 0x92, 0xc0}},
81 {name: "inst=SETCS/reg=R9", inst: SETCS, dst: RegR9, exp: []byte{0x41, 0xf, 0x92, 0xc1}},
82 {name: "inst=SETCS/reg=R13", inst: SETCS, dst: RegR13, exp: []byte{0x41, 0xf, 0x92, 0xc5}},
83 {name: "inst=SETCS/reg=R14", inst: SETCS, dst: RegR14, exp: []byte{0x41, 0xf, 0x92, 0xc6}},
84 {name: "inst=SETCS/reg=R15", inst: SETCS, dst: RegR15, exp: []byte{0x41, 0xf, 0x92, 0xc7}},
85 {name: "inst=SETEQ/reg=AX", inst: SETEQ, dst: RegAX, exp: []byte{0xf, 0x94, 0xc0}},
86 {name: "inst=SETEQ/reg=BX", inst: SETEQ, dst: RegBX, exp: []byte{0xf, 0x94, 0xc3}},
87 {name: "inst=SETEQ/reg=SP", inst: SETEQ, dst: RegSP, exp: []byte{0x40, 0xf, 0x94, 0xc4}},
88 {name: "inst=SETEQ/reg=BP", inst: SETEQ, dst: RegBP, exp: []byte{0x40, 0xf, 0x94, 0xc5}},
89 {name: "inst=SETEQ/reg=SI", inst: SETEQ, dst: RegSI, exp: []byte{0x40, 0xf, 0x94, 0xc6}},
90 {name: "inst=SETEQ/reg=DI", inst: SETEQ, dst: RegDI, exp: []byte{0x40, 0xf, 0x94, 0xc7}},
91 {name: "inst=SETEQ/reg=R8", inst: SETEQ, dst: RegR8, exp: []byte{0x41, 0xf, 0x94, 0xc0}},
92 {name: "inst=SETEQ/reg=R9", inst: SETEQ, dst: RegR9, exp: []byte{0x41, 0xf, 0x94, 0xc1}},
93 {name: "inst=SETEQ/reg=R13", inst: SETEQ, dst: RegR13, exp: []byte{0x41, 0xf, 0x94, 0xc5}},
94 {name: "inst=SETEQ/reg=R14", inst: SETEQ, dst: RegR14, exp: []byte{0x41, 0xf, 0x94, 0xc6}},
95 {name: "inst=SETEQ/reg=R15", inst: SETEQ, dst: RegR15, exp: []byte{0x41, 0xf, 0x94, 0xc7}},
96 {name: "inst=SETGE/reg=AX", inst: SETGE, dst: RegAX, exp: []byte{0xf, 0x9d, 0xc0}},
97 {name: "inst=SETGE/reg=BX", inst: SETGE, dst: RegBX, exp: []byte{0xf, 0x9d, 0xc3}},
98 {name: "inst=SETGE/reg=SP", inst: SETGE, dst: RegSP, exp: []byte{0x40, 0xf, 0x9d, 0xc4}},
99 {name: "inst=SETGE/reg=BP", inst: SETGE, dst: RegBP, exp: []byte{0x40, 0xf, 0x9d, 0xc5}},
100 {name: "inst=SETGE/reg=SI", inst: SETGE, dst: RegSI, exp: []byte{0x40, 0xf, 0x9d, 0xc6}},
101 {name: "inst=SETGE/reg=DI", inst: SETGE, dst: RegDI, exp: []byte{0x40, 0xf, 0x9d, 0xc7}},
102 {name: "inst=SETGE/reg=R8", inst: SETGE, dst: RegR8, exp: []byte{0x41, 0xf, 0x9d, 0xc0}},
103 {name: "inst=SETGE/reg=R9", inst: SETGE, dst: RegR9, exp: []byte{0x41, 0xf, 0x9d, 0xc1}},
104 {name: "inst=SETGE/reg=R13", inst: SETGE, dst: RegR13, exp: []byte{0x41, 0xf, 0x9d, 0xc5}},
105 {name: "inst=SETGE/reg=R14", inst: SETGE, dst: RegR14, exp: []byte{0x41, 0xf, 0x9d, 0xc6}},
106 {name: "inst=SETGE/reg=R15", inst: SETGE, dst: RegR15, exp: []byte{0x41, 0xf, 0x9d, 0xc7}},
107 {name: "inst=SETGT/reg=AX", inst: SETGT, dst: RegAX, exp: []byte{0xf, 0x9f, 0xc0}},
108 {name: "inst=SETGT/reg=BX", inst: SETGT, dst: RegBX, exp: []byte{0xf, 0x9f, 0xc3}},
109 {name: "inst=SETGT/reg=SP", inst: SETGT, dst: RegSP, exp: []byte{0x40, 0xf, 0x9f, 0xc4}},
110 {name: "inst=SETGT/reg=BP", inst: SETGT, dst: RegBP, exp: []byte{0x40, 0xf, 0x9f, 0xc5}},
111 {name: "inst=SETGT/reg=SI", inst: SETGT, dst: RegSI, exp: []byte{0x40, 0xf, 0x9f, 0xc6}},
112 {name: "inst=SETGT/reg=DI", inst: SETGT, dst: RegDI, exp: []byte{0x40, 0xf, 0x9f, 0xc7}},
113 {name: "inst=SETGT/reg=R8", inst: SETGT, dst: RegR8, exp: []byte{0x41, 0xf, 0x9f, 0xc0}},
114 {name: "inst=SETGT/reg=R9", inst: SETGT, dst: RegR9, exp: []byte{0x41, 0xf, 0x9f, 0xc1}},
115 {name: "inst=SETGT/reg=R13", inst: SETGT, dst: RegR13, exp: []byte{0x41, 0xf, 0x9f, 0xc5}},
116 {name: "inst=SETGT/reg=R14", inst: SETGT, dst: RegR14, exp: []byte{0x41, 0xf, 0x9f, 0xc6}},
117 {name: "inst=SETGT/reg=R15", inst: SETGT, dst: RegR15, exp: []byte{0x41, 0xf, 0x9f, 0xc7}},
118 {name: "inst=SETHI/reg=AX", inst: SETHI, dst: RegAX, exp: []byte{0xf, 0x97, 0xc0}},
119 {name: "inst=SETHI/reg=BX", inst: SETHI, dst: RegBX, exp: []byte{0xf, 0x97, 0xc3}},
120 {name: "inst=SETHI/reg=SP", inst: SETHI, dst: RegSP, exp: []byte{0x40, 0xf, 0x97, 0xc4}},
121 {name: "inst=SETHI/reg=BP", inst: SETHI, dst: RegBP, exp: []byte{0x40, 0xf, 0x97, 0xc5}},
122 {name: "inst=SETHI/reg=SI", inst: SETHI, dst: RegSI, exp: []byte{0x40, 0xf, 0x97, 0xc6}},
123 {name: "inst=SETHI/reg=DI", inst: SETHI, dst: RegDI, exp: []byte{0x40, 0xf, 0x97, 0xc7}},
124 {name: "inst=SETHI/reg=R8", inst: SETHI, dst: RegR8, exp: []byte{0x41, 0xf, 0x97, 0xc0}},
125 {name: "inst=SETHI/reg=R9", inst: SETHI, dst: RegR9, exp: []byte{0x41, 0xf, 0x97, 0xc1}},
126 {name: "inst=SETHI/reg=R13", inst: SETHI, dst: RegR13, exp: []byte{0x41, 0xf, 0x97, 0xc5}},
127 {name: "inst=SETHI/reg=R14", inst: SETHI, dst: RegR14, exp: []byte{0x41, 0xf, 0x97, 0xc6}},
128 {name: "inst=SETHI/reg=R15", inst: SETHI, dst: RegR15, exp: []byte{0x41, 0xf, 0x97, 0xc7}},
129 {name: "inst=SETLE/reg=AX", inst: SETLE, dst: RegAX, exp: []byte{0xf, 0x9e, 0xc0}},
130 {name: "inst=SETLE/reg=BX", inst: SETLE, dst: RegBX, exp: []byte{0xf, 0x9e, 0xc3}},
131 {name: "inst=SETLE/reg=SP", inst: SETLE, dst: RegSP, exp: []byte{0x40, 0xf, 0x9e, 0xc4}},
132 {name: "inst=SETLE/reg=BP", inst: SETLE, dst: RegBP, exp: []byte{0x40, 0xf, 0x9e, 0xc5}},
133 {name: "inst=SETLE/reg=SI", inst: SETLE, dst: RegSI, exp: []byte{0x40, 0xf, 0x9e, 0xc6}},
134 {name: "inst=SETLE/reg=DI", inst: SETLE, dst: RegDI, exp: []byte{0x40, 0xf, 0x9e, 0xc7}},
135 {name: "inst=SETLE/reg=R8", inst: SETLE, dst: RegR8, exp: []byte{0x41, 0xf, 0x9e, 0xc0}},
136 {name: "inst=SETLE/reg=R9", inst: SETLE, dst: RegR9, exp: []byte{0x41, 0xf, 0x9e, 0xc1}},
137 {name: "inst=SETLE/reg=R13", inst: SETLE, dst: RegR13, exp: []byte{0x41, 0xf, 0x9e, 0xc5}},
138 {name: "inst=SETLE/reg=R14", inst: SETLE, dst: RegR14, exp: []byte{0x41, 0xf, 0x9e, 0xc6}},
139 {name: "inst=SETLE/reg=R15", inst: SETLE, dst: RegR15, exp: []byte{0x41, 0xf, 0x9e, 0xc7}},
140 {name: "inst=SETLS/reg=AX", inst: SETLS, dst: RegAX, exp: []byte{0xf, 0x96, 0xc0}},
141 {name: "inst=SETLS/reg=BX", inst: SETLS, dst: RegBX, exp: []byte{0xf, 0x96, 0xc3}},
142 {name: "inst=SETLS/reg=SP", inst: SETLS, dst: RegSP, exp: []byte{0x40, 0xf, 0x96, 0xc4}},
143 {name: "inst=SETLS/reg=BP", inst: SETLS, dst: RegBP, exp: []byte{0x40, 0xf, 0x96, 0xc5}},
144 {name: "inst=SETLS/reg=SI", inst: SETLS, dst: RegSI, exp: []byte{0x40, 0xf, 0x96, 0xc6}},
145 {name: "inst=SETLS/reg=DI", inst: SETLS, dst: RegDI, exp: []byte{0x40, 0xf, 0x96, 0xc7}},
146 {name: "inst=SETLS/reg=R8", inst: SETLS, dst: RegR8, exp: []byte{0x41, 0xf, 0x96, 0xc0}},
147 {name: "inst=SETLS/reg=R9", inst: SETLS, dst: RegR9, exp: []byte{0x41, 0xf, 0x96, 0xc1}},
148 {name: "inst=SETLS/reg=R13", inst: SETLS, dst: RegR13, exp: []byte{0x41, 0xf, 0x96, 0xc5}},
149 {name: "inst=SETLS/reg=R14", inst: SETLS, dst: RegR14, exp: []byte{0x41, 0xf, 0x96, 0xc6}},
150 {name: "inst=SETLS/reg=R15", inst: SETLS, dst: RegR15, exp: []byte{0x41, 0xf, 0x96, 0xc7}},
151 {name: "inst=SETLT/reg=AX", inst: SETLT, dst: RegAX, exp: []byte{0xf, 0x9c, 0xc0}},
152 {name: "inst=SETLT/reg=BX", inst: SETLT, dst: RegBX, exp: []byte{0xf, 0x9c, 0xc3}},
153 {name: "inst=SETLT/reg=SP", inst: SETLT, dst: RegSP, exp: []byte{0x40, 0xf, 0x9c, 0xc4}},
154 {name: "inst=SETLT/reg=BP", inst: SETLT, dst: RegBP, exp: []byte{0x40, 0xf, 0x9c, 0xc5}},
155 {name: "inst=SETLT/reg=SI", inst: SETLT, dst: RegSI, exp: []byte{0x40, 0xf, 0x9c, 0xc6}},
156 {name: "inst=SETLT/reg=DI", inst: SETLT, dst: RegDI, exp: []byte{0x40, 0xf, 0x9c, 0xc7}},
157 {name: "inst=SETLT/reg=R8", inst: SETLT, dst: RegR8, exp: []byte{0x41, 0xf, 0x9c, 0xc0}},
158 {name: "inst=SETLT/reg=R9", inst: SETLT, dst: RegR9, exp: []byte{0x41, 0xf, 0x9c, 0xc1}},
159 {name: "inst=SETLT/reg=R13", inst: SETLT, dst: RegR13, exp: []byte{0x41, 0xf, 0x9c, 0xc5}},
160 {name: "inst=SETLT/reg=R14", inst: SETLT, dst: RegR14, exp: []byte{0x41, 0xf, 0x9c, 0xc6}},
161 {name: "inst=SETLT/reg=R15", inst: SETLT, dst: RegR15, exp: []byte{0x41, 0xf, 0x9c, 0xc7}},
162 {name: "inst=SETNE/reg=AX", inst: SETNE, dst: RegAX, exp: []byte{0xf, 0x95, 0xc0}},
163 {name: "inst=SETNE/reg=BX", inst: SETNE, dst: RegBX, exp: []byte{0xf, 0x95, 0xc3}},
164 {name: "inst=SETNE/reg=SP", inst: SETNE, dst: RegSP, exp: []byte{0x40, 0xf, 0x95, 0xc4}},
165 {name: "inst=SETNE/reg=BP", inst: SETNE, dst: RegBP, exp: []byte{0x40, 0xf, 0x95, 0xc5}},
166 {name: "inst=SETNE/reg=SI", inst: SETNE, dst: RegSI, exp: []byte{0x40, 0xf, 0x95, 0xc6}},
167 {name: "inst=SETNE/reg=DI", inst: SETNE, dst: RegDI, exp: []byte{0x40, 0xf, 0x95, 0xc7}},
168 {name: "inst=SETNE/reg=R8", inst: SETNE, dst: RegR8, exp: []byte{0x41, 0xf, 0x95, 0xc0}},
169 {name: "inst=SETNE/reg=R9", inst: SETNE, dst: RegR9, exp: []byte{0x41, 0xf, 0x95, 0xc1}},
170 {name: "inst=SETNE/reg=R13", inst: SETNE, dst: RegR13, exp: []byte{0x41, 0xf, 0x95, 0xc5}},
171 {name: "inst=SETNE/reg=R14", inst: SETNE, dst: RegR14, exp: []byte{0x41, 0xf, 0x95, 0xc6}},
172 {name: "inst=SETNE/reg=R15", inst: SETNE, dst: RegR15, exp: []byte{0x41, 0xf, 0x95, 0xc7}},
173 {name: "inst=SETPC/reg=AX", inst: SETPC, dst: RegAX, exp: []byte{0xf, 0x9b, 0xc0}},
174 {name: "inst=SETPC/reg=BX", inst: SETPC, dst: RegBX, exp: []byte{0xf, 0x9b, 0xc3}},
175 {name: "inst=SETPC/reg=SP", inst: SETPC, dst: RegSP, exp: []byte{0x40, 0xf, 0x9b, 0xc4}},
176 {name: "inst=SETPC/reg=BP", inst: SETPC, dst: RegBP, exp: []byte{0x40, 0xf, 0x9b, 0xc5}},
177 {name: "inst=SETPC/reg=SI", inst: SETPC, dst: RegSI, exp: []byte{0x40, 0xf, 0x9b, 0xc6}},
178 {name: "inst=SETPC/reg=DI", inst: SETPC, dst: RegDI, exp: []byte{0x40, 0xf, 0x9b, 0xc7}},
179 {name: "inst=SETPC/reg=R8", inst: SETPC, dst: RegR8, exp: []byte{0x41, 0xf, 0x9b, 0xc0}},
180 {name: "inst=SETPC/reg=R9", inst: SETPC, dst: RegR9, exp: []byte{0x41, 0xf, 0x9b, 0xc1}},
181 {name: "inst=SETPC/reg=R13", inst: SETPC, dst: RegR13, exp: []byte{0x41, 0xf, 0x9b, 0xc5}},
182 {name: "inst=SETPC/reg=R14", inst: SETPC, dst: RegR14, exp: []byte{0x41, 0xf, 0x9b, 0xc6}},
183 {name: "inst=SETPC/reg=R15", inst: SETPC, dst: RegR15, exp: []byte{0x41, 0xf, 0x9b, 0xc7}},
184 {name: "inst=SETPS/reg=AX", inst: SETPS, dst: RegAX, exp: []byte{0xf, 0x9a, 0xc0}},
185 {name: "inst=SETPS/reg=BX", inst: SETPS, dst: RegBX, exp: []byte{0xf, 0x9a, 0xc3}},
186 {name: "inst=SETPS/reg=SP", inst: SETPS, dst: RegSP, exp: []byte{0x40, 0xf, 0x9a, 0xc4}},
187 {name: "inst=SETPS/reg=BP", inst: SETPS, dst: RegBP, exp: []byte{0x40, 0xf, 0x9a, 0xc5}},
188 {name: "inst=SETPS/reg=SI", inst: SETPS, dst: RegSI, exp: []byte{0x40, 0xf, 0x9a, 0xc6}},
189 {name: "inst=SETPS/reg=DI", inst: SETPS, dst: RegDI, exp: []byte{0x40, 0xf, 0x9a, 0xc7}},
190 {name: "inst=SETPS/reg=R8", inst: SETPS, dst: RegR8, exp: []byte{0x41, 0xf, 0x9a, 0xc0}},
191 {name: "inst=SETPS/reg=R9", inst: SETPS, dst: RegR9, exp: []byte{0x41, 0xf, 0x9a, 0xc1}},
192 {name: "inst=SETPS/reg=R13", inst: SETPS, dst: RegR13, exp: []byte{0x41, 0xf, 0x9a, 0xc5}},
193 {name: "inst=SETPS/reg=R14", inst: SETPS, dst: RegR14, exp: []byte{0x41, 0xf, 0x9a, 0xc6}},
194 {name: "inst=SETPS/reg=R15", inst: SETPS, dst: RegR15, exp: []byte{0x41, 0xf, 0x9a, 0xc7}},
195 {name: "inst=NEGQ/reg=AX", inst: NEGQ, dst: RegAX, exp: []byte{0x48, 0xf7, 0xd8}},
196 {name: "inst=NEGQ/reg=BX", inst: NEGQ, dst: RegBX, exp: []byte{0x48, 0xf7, 0xdb}},
197 {name: "inst=NEGQ/reg=SP", inst: NEGQ, dst: RegSP, exp: []byte{0x48, 0xf7, 0xdc}},
198 {name: "inst=NEGQ/reg=BP", inst: NEGQ, dst: RegBP, exp: []byte{0x48, 0xf7, 0xdd}},
199 {name: "inst=NEGQ/reg=SI", inst: NEGQ, dst: RegSI, exp: []byte{0x48, 0xf7, 0xde}},
200 {name: "inst=NEGQ/reg=DI", inst: NEGQ, dst: RegDI, exp: []byte{0x48, 0xf7, 0xdf}},
201 {name: "inst=NEGQ/reg=R8", inst: NEGQ, dst: RegR8, exp: []byte{0x49, 0xf7, 0xd8}},
202 {name: "inst=NEGQ/reg=R9", inst: NEGQ, dst: RegR9, exp: []byte{0x49, 0xf7, 0xd9}},
203 {name: "inst=NEGQ/reg=R13", inst: NEGQ, dst: RegR13, exp: []byte{0x49, 0xf7, 0xdd}},
204 {name: "inst=NEGQ/reg=R14", inst: NEGQ, dst: RegR14, exp: []byte{0x49, 0xf7, 0xde}},
205 {name: "inst=NEGQ/reg=R15", inst: NEGQ, dst: RegR15, exp: []byte{0x49, 0xf7, 0xdf}},
206 {name: "inst=INCQ/reg=AX", inst: INCQ, dst: RegAX, exp: []byte{0x48, 0xff, 0xc0}},
207 {name: "inst=INCQ/reg=BX", inst: INCQ, dst: RegBX, exp: []byte{0x48, 0xff, 0xc3}},
208 {name: "inst=INCQ/reg=SP", inst: INCQ, dst: RegSP, exp: []byte{0x48, 0xff, 0xc4}},
209 {name: "inst=INCQ/reg=BP", inst: INCQ, dst: RegBP, exp: []byte{0x48, 0xff, 0xc5}},
210 {name: "inst=INCQ/reg=SI", inst: INCQ, dst: RegSI, exp: []byte{0x48, 0xff, 0xc6}},
211 {name: "inst=INCQ/reg=DI", inst: INCQ, dst: RegDI, exp: []byte{0x48, 0xff, 0xc7}},
212 {name: "inst=INCQ/reg=R8", inst: INCQ, dst: RegR8, exp: []byte{0x49, 0xff, 0xc0}},
213 {name: "inst=INCQ/reg=R9", inst: INCQ, dst: RegR9, exp: []byte{0x49, 0xff, 0xc1}},
214 {name: "inst=INCQ/reg=R13", inst: INCQ, dst: RegR13, exp: []byte{0x49, 0xff, 0xc5}},
215 {name: "inst=INCQ/reg=R14", inst: INCQ, dst: RegR14, exp: []byte{0x49, 0xff, 0xc6}},
216 {name: "inst=INCQ/reg=R15", inst: INCQ, dst: RegR15, exp: []byte{0x49, 0xff, 0xc7}},
217 {name: "inst=DECQ/reg=AX", inst: DECQ, dst: RegAX, exp: []byte{0x48, 0xff, 0xc8}},
218 {name: "inst=DECQ/reg=BX", inst: DECQ, dst: RegBX, exp: []byte{0x48, 0xff, 0xcb}},
219 {name: "inst=DECQ/reg=SP", inst: DECQ, dst: RegSP, exp: []byte{0x48, 0xff, 0xcc}},
220 {name: "inst=DECQ/reg=BP", inst: DECQ, dst: RegBP, exp: []byte{0x48, 0xff, 0xcd}},
221 {name: "inst=DECQ/reg=SI", inst: DECQ, dst: RegSI, exp: []byte{0x48, 0xff, 0xce}},
222 {name: "inst=DECQ/reg=DI", inst: DECQ, dst: RegDI, exp: []byte{0x48, 0xff, 0xcf}},
223 {name: "inst=DECQ/reg=R8", inst: DECQ, dst: RegR8, exp: []byte{0x49, 0xff, 0xc8}},
224 {name: "inst=DECQ/reg=R9", inst: DECQ, dst: RegR9, exp: []byte{0x49, 0xff, 0xc9}},
225 {name: "inst=DECQ/reg=R13", inst: DECQ, dst: RegR13, exp: []byte{0x49, 0xff, 0xcd}},
226 {name: "inst=DECQ/reg=R14", inst: DECQ, dst: RegR14, exp: []byte{0x49, 0xff, 0xce}},
227 {name: "inst=DECQ/reg=R15", inst: DECQ, dst: RegR15, exp: []byte{0x49, 0xff, 0xcf}},
228 }
229
230 code := asm.CodeSegment{}
231 defer func() { require.NoError(t, code.Unmap()) }()
232
233 for _, tc := range tests {
234 tc := tc
235 a := NewAssembler()
236 buf := code.NextCodeSection()
237 err := a.encodeNoneToRegister(buf, &nodeImpl{instruction: tc.inst, dstReg: tc.dst})
238 require.NoError(t, err, tc.name)
239 require.Equal(t, tc.exp, buf.Bytes(), tc.name)
240 }
241 }
242
243 func TestAssemblerImpl_EncodeNoneToMemory(t *testing.T) {
244 t.Run("error", func(t *testing.T) {
245 tests := []struct {
246 n *nodeImpl
247 expErr string
248 }{
249 {
250 n: &nodeImpl{instruction: ADDL, types: operandTypesNoneToMemory, dstReg: RegAX},
251 expErr: "ADDL is unsupported for NoneToMemory type",
252 },
253 }
254
255 for _, tt := range tests {
256 tc := tt
257 t.Run(tc.expErr, func(t *testing.T) {
258 code := asm.CodeSegment{}
259 defer func() { require.NoError(t, code.Unmap()) }()
260
261 tc := tc
262 a := NewAssembler()
263 buf := code.NextCodeSection()
264 err := a.encodeNoneToMemory(buf, tc.n)
265 require.EqualError(t, err, tc.expErr)
266 })
267 }
268 })
269
270 tests := []struct {
271 name string
272 inst asm.Instruction
273 dst asm.Register
274 dstOffset int64
275 exp []byte
276 }{
277 {name: "inst=DECQ/reg=AX/offset=0", inst: DECQ, dst: RegAX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x8}},
278 {name: "inst=DECQ/reg=AX/offset=1", inst: DECQ, dst: RegAX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x48, 0x1}},
279 {name: "inst=DECQ/reg=AX/offset=-1", inst: DECQ, dst: RegAX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x48, 0xff}},
280 {name: "inst=DECQ/reg=AX/offset=1243", inst: DECQ, dst: RegAX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x88, 0xdb, 0x4, 0x0, 0x0}},
281 {name: "inst=DECQ/reg=AX/offset=2147483647", inst: DECQ, dst: RegAX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x88, 0xff, 0xff, 0xff, 0x7f}},
282 {name: "inst=DECQ/reg=AX/offset=-32768", inst: DECQ, dst: RegAX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x88, 0x0, 0x80, 0xff, 0xff}},
283 {name: "inst=DECQ/reg=BX/offset=0", inst: DECQ, dst: RegBX, dstOffset: 0, exp: []byte{0x48, 0xff, 0xb}},
284 {name: "inst=DECQ/reg=BX/offset=1", inst: DECQ, dst: RegBX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4b, 0x1}},
285 {name: "inst=DECQ/reg=BX/offset=-1", inst: DECQ, dst: RegBX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4b, 0xff}},
286 {name: "inst=DECQ/reg=BX/offset=1243", inst: DECQ, dst: RegBX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8b, 0xdb, 0x4, 0x0, 0x0}},
287 {name: "inst=DECQ/reg=BX/offset=2147483647", inst: DECQ, dst: RegBX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8b, 0xff, 0xff, 0xff, 0x7f}},
288 {name: "inst=DECQ/reg=BX/offset=-32768", inst: DECQ, dst: RegBX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8b, 0x0, 0x80, 0xff, 0xff}},
289 {name: "inst=DECQ/reg=SP/offset=0", inst: DECQ, dst: RegSP, dstOffset: 0, exp: []byte{0x48, 0xff, 0xc, 0x24}},
290 {name: "inst=DECQ/reg=SP/offset=1", inst: DECQ, dst: RegSP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4c, 0x24, 0x1}},
291 {name: "inst=DECQ/reg=SP/offset=-1", inst: DECQ, dst: RegSP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4c, 0x24, 0xff}},
292 {name: "inst=DECQ/reg=SP/offset=1243", inst: DECQ, dst: RegSP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0xdb, 0x4, 0x0, 0x0}},
293 {name: "inst=DECQ/reg=SP/offset=2147483647", inst: DECQ, dst: RegSP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0xff, 0xff, 0xff, 0x7f}},
294 {name: "inst=DECQ/reg=SP/offset=-32768", inst: DECQ, dst: RegSP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8c, 0x24, 0x0, 0x80, 0xff, 0xff}},
295 {name: "inst=DECQ/reg=BP/offset=0", inst: DECQ, dst: RegBP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x4d, 0x0}},
296 {name: "inst=DECQ/reg=BP/offset=1", inst: DECQ, dst: RegBP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4d, 0x1}},
297 {name: "inst=DECQ/reg=BP/offset=-1", inst: DECQ, dst: RegBP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4d, 0xff}},
298 {name: "inst=DECQ/reg=BP/offset=1243", inst: DECQ, dst: RegBP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8d, 0xdb, 0x4, 0x0, 0x0}},
299 {name: "inst=DECQ/reg=BP/offset=2147483647", inst: DECQ, dst: RegBP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8d, 0xff, 0xff, 0xff, 0x7f}},
300 {name: "inst=DECQ/reg=BP/offset=-32768", inst: DECQ, dst: RegBP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8d, 0x0, 0x80, 0xff, 0xff}},
301 {name: "inst=DECQ/reg=SI/offset=0", inst: DECQ, dst: RegSI, dstOffset: 0, exp: []byte{0x48, 0xff, 0xe}},
302 {name: "inst=DECQ/reg=SI/offset=1", inst: DECQ, dst: RegSI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4e, 0x1}},
303 {name: "inst=DECQ/reg=SI/offset=-1", inst: DECQ, dst: RegSI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4e, 0xff}},
304 {name: "inst=DECQ/reg=SI/offset=1243", inst: DECQ, dst: RegSI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8e, 0xdb, 0x4, 0x0, 0x0}},
305 {name: "inst=DECQ/reg=SI/offset=2147483647", inst: DECQ, dst: RegSI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8e, 0xff, 0xff, 0xff, 0x7f}},
306 {name: "inst=DECQ/reg=SI/offset=-32768", inst: DECQ, dst: RegSI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8e, 0x0, 0x80, 0xff, 0xff}},
307 {name: "inst=DECQ/reg=DI/offset=0", inst: DECQ, dst: RegDI, dstOffset: 0, exp: []byte{0x48, 0xff, 0xf}},
308 {name: "inst=DECQ/reg=DI/offset=1", inst: DECQ, dst: RegDI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x4f, 0x1}},
309 {name: "inst=DECQ/reg=DI/offset=-1", inst: DECQ, dst: RegDI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x4f, 0xff}},
310 {name: "inst=DECQ/reg=DI/offset=1243", inst: DECQ, dst: RegDI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x8f, 0xdb, 0x4, 0x0, 0x0}},
311 {name: "inst=DECQ/reg=DI/offset=2147483647", inst: DECQ, dst: RegDI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x8f, 0xff, 0xff, 0xff, 0x7f}},
312 {name: "inst=DECQ/reg=DI/offset=-32768", inst: DECQ, dst: RegDI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x8f, 0x0, 0x80, 0xff, 0xff}},
313 {name: "inst=DECQ/reg=R8/offset=0", inst: DECQ, dst: RegR8, dstOffset: 0, exp: []byte{0x49, 0xff, 0x8}},
314 {name: "inst=DECQ/reg=R8/offset=1", inst: DECQ, dst: RegR8, dstOffset: 1, exp: []byte{0x49, 0xff, 0x48, 0x1}},
315 {name: "inst=DECQ/reg=R8/offset=-1", inst: DECQ, dst: RegR8, dstOffset: -1, exp: []byte{0x49, 0xff, 0x48, 0xff}},
316 {name: "inst=DECQ/reg=R8/offset=1243", inst: DECQ, dst: RegR8, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x88, 0xdb, 0x4, 0x0, 0x0}},
317 {name: "inst=DECQ/reg=R8/offset=2147483647", inst: DECQ, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x88, 0xff, 0xff, 0xff, 0x7f}},
318 {name: "inst=DECQ/reg=R8/offset=-32768", inst: DECQ, dst: RegR8, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x88, 0x0, 0x80, 0xff, 0xff}},
319 {name: "inst=DECQ/reg=R9/offset=0", inst: DECQ, dst: RegR9, dstOffset: 0, exp: []byte{0x49, 0xff, 0x9}},
320 {name: "inst=DECQ/reg=R9/offset=1", inst: DECQ, dst: RegR9, dstOffset: 1, exp: []byte{0x49, 0xff, 0x49, 0x1}},
321 {name: "inst=DECQ/reg=R9/offset=-1", inst: DECQ, dst: RegR9, dstOffset: -1, exp: []byte{0x49, 0xff, 0x49, 0xff}},
322 {name: "inst=DECQ/reg=R9/offset=1243", inst: DECQ, dst: RegR9, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x89, 0xdb, 0x4, 0x0, 0x0}},
323 {name: "inst=DECQ/reg=R9/offset=2147483647", inst: DECQ, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x89, 0xff, 0xff, 0xff, 0x7f}},
324 {name: "inst=DECQ/reg=R9/offset=-32768", inst: DECQ, dst: RegR9, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x89, 0x0, 0x80, 0xff, 0xff}},
325 {name: "inst=DECQ/reg=R13/offset=0", inst: DECQ, dst: RegR13, dstOffset: 0, exp: []byte{0x49, 0xff, 0x4d, 0x0}},
326 {name: "inst=DECQ/reg=R13/offset=1", inst: DECQ, dst: RegR13, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4d, 0x1}},
327 {name: "inst=DECQ/reg=R13/offset=-1", inst: DECQ, dst: RegR13, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4d, 0xff}},
328 {name: "inst=DECQ/reg=R13/offset=1243", inst: DECQ, dst: RegR13, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8d, 0xdb, 0x4, 0x0, 0x0}},
329 {name: "inst=DECQ/reg=R13/offset=2147483647", inst: DECQ, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8d, 0xff, 0xff, 0xff, 0x7f}},
330 {name: "inst=DECQ/reg=R13/offset=-32768", inst: DECQ, dst: RegR13, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8d, 0x0, 0x80, 0xff, 0xff}},
331 {name: "inst=DECQ/reg=R14/offset=0", inst: DECQ, dst: RegR14, dstOffset: 0, exp: []byte{0x49, 0xff, 0xe}},
332 {name: "inst=DECQ/reg=R14/offset=1", inst: DECQ, dst: RegR14, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4e, 0x1}},
333 {name: "inst=DECQ/reg=R14/offset=-1", inst: DECQ, dst: RegR14, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4e, 0xff}},
334 {name: "inst=DECQ/reg=R14/offset=1243", inst: DECQ, dst: RegR14, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8e, 0xdb, 0x4, 0x0, 0x0}},
335 {name: "inst=DECQ/reg=R14/offset=2147483647", inst: DECQ, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8e, 0xff, 0xff, 0xff, 0x7f}},
336 {name: "inst=DECQ/reg=R14/offset=-32768", inst: DECQ, dst: RegR14, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8e, 0x0, 0x80, 0xff, 0xff}},
337 {name: "inst=DECQ/reg=R15/offset=0", inst: DECQ, dst: RegR15, dstOffset: 0, exp: []byte{0x49, 0xff, 0xf}},
338 {name: "inst=DECQ/reg=R15/offset=1", inst: DECQ, dst: RegR15, dstOffset: 1, exp: []byte{0x49, 0xff, 0x4f, 0x1}},
339 {name: "inst=DECQ/reg=R15/offset=-1", inst: DECQ, dst: RegR15, dstOffset: -1, exp: []byte{0x49, 0xff, 0x4f, 0xff}},
340 {name: "inst=DECQ/reg=R15/offset=1243", inst: DECQ, dst: RegR15, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x8f, 0xdb, 0x4, 0x0, 0x0}},
341 {name: "inst=DECQ/reg=R15/offset=2147483647", inst: DECQ, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x8f, 0xff, 0xff, 0xff, 0x7f}},
342 {name: "inst=DECQ/reg=R15/offset=-32768", inst: DECQ, dst: RegR15, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x8f, 0x0, 0x80, 0xff, 0xff}},
343 {name: "inst=INCQ/reg=AX/offset=0", inst: INCQ, dst: RegAX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x0}},
344 {name: "inst=INCQ/reg=AX/offset=1", inst: INCQ, dst: RegAX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x40, 0x1}},
345 {name: "inst=INCQ/reg=AX/offset=-1", inst: INCQ, dst: RegAX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x40, 0xff}},
346 {name: "inst=INCQ/reg=AX/offset=1243", inst: INCQ, dst: RegAX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x80, 0xdb, 0x4, 0x0, 0x0}},
347 {name: "inst=INCQ/reg=AX/offset=2147483647", inst: INCQ, dst: RegAX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x80, 0xff, 0xff, 0xff, 0x7f}},
348 {name: "inst=INCQ/reg=AX/offset=-32768", inst: INCQ, dst: RegAX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x80, 0x0, 0x80, 0xff, 0xff}},
349 {name: "inst=INCQ/reg=BX/offset=0", inst: INCQ, dst: RegBX, dstOffset: 0, exp: []byte{0x48, 0xff, 0x3}},
350 {name: "inst=INCQ/reg=BX/offset=1", inst: INCQ, dst: RegBX, dstOffset: 1, exp: []byte{0x48, 0xff, 0x43, 0x1}},
351 {name: "inst=INCQ/reg=BX/offset=-1", inst: INCQ, dst: RegBX, dstOffset: -1, exp: []byte{0x48, 0xff, 0x43, 0xff}},
352 {name: "inst=INCQ/reg=BX/offset=1243", inst: INCQ, dst: RegBX, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x83, 0xdb, 0x4, 0x0, 0x0}},
353 {name: "inst=INCQ/reg=BX/offset=2147483647", inst: INCQ, dst: RegBX, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x83, 0xff, 0xff, 0xff, 0x7f}},
354 {name: "inst=INCQ/reg=BX/offset=-32768", inst: INCQ, dst: RegBX, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x83, 0x0, 0x80, 0xff, 0xff}},
355 {name: "inst=INCQ/reg=SP/offset=0", inst: INCQ, dst: RegSP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x4, 0x24}},
356 {name: "inst=INCQ/reg=SP/offset=1", inst: INCQ, dst: RegSP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x44, 0x24, 0x1}},
357 {name: "inst=INCQ/reg=SP/offset=-1", inst: INCQ, dst: RegSP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x44, 0x24, 0xff}},
358 {name: "inst=INCQ/reg=SP/offset=1243", inst: INCQ, dst: RegSP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x84, 0x24, 0xdb, 0x4, 0x0, 0x0}},
359 {name: "inst=INCQ/reg=SP/offset=2147483647", inst: INCQ, dst: RegSP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x84, 0x24, 0xff, 0xff, 0xff, 0x7f}},
360 {name: "inst=INCQ/reg=SP/offset=-32768", inst: INCQ, dst: RegSP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x84, 0x24, 0x0, 0x80, 0xff, 0xff}},
361 {name: "inst=INCQ/reg=BP/offset=0", inst: INCQ, dst: RegBP, dstOffset: 0, exp: []byte{0x48, 0xff, 0x45, 0x0}},
362 {name: "inst=INCQ/reg=BP/offset=1", inst: INCQ, dst: RegBP, dstOffset: 1, exp: []byte{0x48, 0xff, 0x45, 0x1}},
363 {name: "inst=INCQ/reg=BP/offset=-1", inst: INCQ, dst: RegBP, dstOffset: -1, exp: []byte{0x48, 0xff, 0x45, 0xff}},
364 {name: "inst=INCQ/reg=BP/offset=1243", inst: INCQ, dst: RegBP, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x85, 0xdb, 0x4, 0x0, 0x0}},
365 {name: "inst=INCQ/reg=BP/offset=2147483647", inst: INCQ, dst: RegBP, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x85, 0xff, 0xff, 0xff, 0x7f}},
366 {name: "inst=INCQ/reg=BP/offset=-32768", inst: INCQ, dst: RegBP, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x85, 0x0, 0x80, 0xff, 0xff}},
367 {name: "inst=INCQ/reg=SI/offset=0", inst: INCQ, dst: RegSI, dstOffset: 0, exp: []byte{0x48, 0xff, 0x6}},
368 {name: "inst=INCQ/reg=SI/offset=1", inst: INCQ, dst: RegSI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x46, 0x1}},
369 {name: "inst=INCQ/reg=SI/offset=-1", inst: INCQ, dst: RegSI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x46, 0xff}},
370 {name: "inst=INCQ/reg=SI/offset=1243", inst: INCQ, dst: RegSI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x86, 0xdb, 0x4, 0x0, 0x0}},
371 {name: "inst=INCQ/reg=SI/offset=2147483647", inst: INCQ, dst: RegSI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x86, 0xff, 0xff, 0xff, 0x7f}},
372 {name: "inst=INCQ/reg=SI/offset=-32768", inst: INCQ, dst: RegSI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x86, 0x0, 0x80, 0xff, 0xff}},
373 {name: "inst=INCQ/reg=DI/offset=0", inst: INCQ, dst: RegDI, dstOffset: 0, exp: []byte{0x48, 0xff, 0x7}},
374 {name: "inst=INCQ/reg=DI/offset=1", inst: INCQ, dst: RegDI, dstOffset: 1, exp: []byte{0x48, 0xff, 0x47, 0x1}},
375 {name: "inst=INCQ/reg=DI/offset=-1", inst: INCQ, dst: RegDI, dstOffset: -1, exp: []byte{0x48, 0xff, 0x47, 0xff}},
376 {name: "inst=INCQ/reg=DI/offset=1243", inst: INCQ, dst: RegDI, dstOffset: 1243, exp: []byte{0x48, 0xff, 0x87, 0xdb, 0x4, 0x0, 0x0}},
377 {name: "inst=INCQ/reg=DI/offset=2147483647", inst: INCQ, dst: RegDI, dstOffset: 2147483647, exp: []byte{0x48, 0xff, 0x87, 0xff, 0xff, 0xff, 0x7f}},
378 {name: "inst=INCQ/reg=DI/offset=-32768", inst: INCQ, dst: RegDI, dstOffset: -32768, exp: []byte{0x48, 0xff, 0x87, 0x0, 0x80, 0xff, 0xff}},
379 {name: "inst=INCQ/reg=R8/offset=0", inst: INCQ, dst: RegR8, dstOffset: 0, exp: []byte{0x49, 0xff, 0x0}},
380 {name: "inst=INCQ/reg=R8/offset=1", inst: INCQ, dst: RegR8, dstOffset: 1, exp: []byte{0x49, 0xff, 0x40, 0x1}},
381 {name: "inst=INCQ/reg=R8/offset=-1", inst: INCQ, dst: RegR8, dstOffset: -1, exp: []byte{0x49, 0xff, 0x40, 0xff}},
382 {name: "inst=INCQ/reg=R8/offset=1243", inst: INCQ, dst: RegR8, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x80, 0xdb, 0x4, 0x0, 0x0}},
383 {name: "inst=INCQ/reg=R8/offset=2147483647", inst: INCQ, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x80, 0xff, 0xff, 0xff, 0x7f}},
384 {name: "inst=INCQ/reg=R8/offset=-32768", inst: INCQ, dst: RegR8, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x80, 0x0, 0x80, 0xff, 0xff}},
385 {name: "inst=INCQ/reg=R9/offset=0", inst: INCQ, dst: RegR9, dstOffset: 0, exp: []byte{0x49, 0xff, 0x1}},
386 {name: "inst=INCQ/reg=R9/offset=1", inst: INCQ, dst: RegR9, dstOffset: 1, exp: []byte{0x49, 0xff, 0x41, 0x1}},
387 {name: "inst=INCQ/reg=R9/offset=-1", inst: INCQ, dst: RegR9, dstOffset: -1, exp: []byte{0x49, 0xff, 0x41, 0xff}},
388 {name: "inst=INCQ/reg=R9/offset=1243", inst: INCQ, dst: RegR9, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x81, 0xdb, 0x4, 0x0, 0x0}},
389 {name: "inst=INCQ/reg=R9/offset=2147483647", inst: INCQ, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x81, 0xff, 0xff, 0xff, 0x7f}},
390 {name: "inst=INCQ/reg=R9/offset=-32768", inst: INCQ, dst: RegR9, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x81, 0x0, 0x80, 0xff, 0xff}},
391 {name: "inst=INCQ/reg=R13/offset=0", inst: INCQ, dst: RegR13, dstOffset: 0, exp: []byte{0x49, 0xff, 0x45, 0x0}},
392 {name: "inst=INCQ/reg=R13/offset=1", inst: INCQ, dst: RegR13, dstOffset: 1, exp: []byte{0x49, 0xff, 0x45, 0x1}},
393 {name: "inst=INCQ/reg=R13/offset=-1", inst: INCQ, dst: RegR13, dstOffset: -1, exp: []byte{0x49, 0xff, 0x45, 0xff}},
394 {name: "inst=INCQ/reg=R13/offset=1243", inst: INCQ, dst: RegR13, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x85, 0xdb, 0x4, 0x0, 0x0}},
395 {name: "inst=INCQ/reg=R13/offset=2147483647", inst: INCQ, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x85, 0xff, 0xff, 0xff, 0x7f}},
396 {name: "inst=INCQ/reg=R13/offset=-32768", inst: INCQ, dst: RegR13, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x85, 0x0, 0x80, 0xff, 0xff}},
397 {name: "inst=INCQ/reg=R14/offset=0", inst: INCQ, dst: RegR14, dstOffset: 0, exp: []byte{0x49, 0xff, 0x6}},
398 {name: "inst=INCQ/reg=R14/offset=1", inst: INCQ, dst: RegR14, dstOffset: 1, exp: []byte{0x49, 0xff, 0x46, 0x1}},
399 {name: "inst=INCQ/reg=R14/offset=-1", inst: INCQ, dst: RegR14, dstOffset: -1, exp: []byte{0x49, 0xff, 0x46, 0xff}},
400 {name: "inst=INCQ/reg=R14/offset=1243", inst: INCQ, dst: RegR14, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x86, 0xdb, 0x4, 0x0, 0x0}},
401 {name: "inst=INCQ/reg=R14/offset=2147483647", inst: INCQ, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x86, 0xff, 0xff, 0xff, 0x7f}},
402 {name: "inst=INCQ/reg=R14/offset=-32768", inst: INCQ, dst: RegR14, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x86, 0x0, 0x80, 0xff, 0xff}},
403 {name: "inst=INCQ/reg=R15/offset=0", inst: INCQ, dst: RegR15, dstOffset: 0, exp: []byte{0x49, 0xff, 0x7}},
404 {name: "inst=INCQ/reg=R15/offset=1", inst: INCQ, dst: RegR15, dstOffset: 1, exp: []byte{0x49, 0xff, 0x47, 0x1}},
405 {name: "inst=INCQ/reg=R15/offset=-1", inst: INCQ, dst: RegR15, dstOffset: -1, exp: []byte{0x49, 0xff, 0x47, 0xff}},
406 {name: "inst=INCQ/reg=R15/offset=1243", inst: INCQ, dst: RegR15, dstOffset: 1243, exp: []byte{0x49, 0xff, 0x87, 0xdb, 0x4, 0x0, 0x0}},
407 {name: "inst=INCQ/reg=R15/offset=2147483647", inst: INCQ, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x49, 0xff, 0x87, 0xff, 0xff, 0xff, 0x7f}},
408 {name: "inst=INCQ/reg=R15/offset=-32768", inst: INCQ, dst: RegR15, dstOffset: -32768, exp: []byte{0x49, 0xff, 0x87, 0x0, 0x80, 0xff, 0xff}},
409 {name: "inst=JMP/reg=AX/offset=0", inst: JMP, dst: RegAX, dstOffset: 0, exp: []byte{0xff, 0x20}},
410 {name: "inst=JMP/reg=AX/offset=1", inst: JMP, dst: RegAX, dstOffset: 1, exp: []byte{0xff, 0x60, 0x1}},
411 {name: "inst=JMP/reg=AX/offset=-1", inst: JMP, dst: RegAX, dstOffset: -1, exp: []byte{0xff, 0x60, 0xff}},
412 {name: "inst=JMP/reg=AX/offset=1243", inst: JMP, dst: RegAX, dstOffset: 1243, exp: []byte{0xff, 0xa0, 0xdb, 0x4, 0x0, 0x0}},
413 {name: "inst=JMP/reg=AX/offset=2147483647", inst: JMP, dst: RegAX, dstOffset: 2147483647, exp: []byte{0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f}},
414 {name: "inst=JMP/reg=AX/offset=-32768", inst: JMP, dst: RegAX, dstOffset: -32768, exp: []byte{0xff, 0xa0, 0x0, 0x80, 0xff, 0xff}},
415 {name: "inst=JMP/reg=BX/offset=0", inst: JMP, dst: RegBX, dstOffset: 0, exp: []byte{0xff, 0x23}},
416 {name: "inst=JMP/reg=BX/offset=1", inst: JMP, dst: RegBX, dstOffset: 1, exp: []byte{0xff, 0x63, 0x1}},
417 {name: "inst=JMP/reg=BX/offset=-1", inst: JMP, dst: RegBX, dstOffset: -1, exp: []byte{0xff, 0x63, 0xff}},
418 {name: "inst=JMP/reg=BX/offset=1243", inst: JMP, dst: RegBX, dstOffset: 1243, exp: []byte{0xff, 0xa3, 0xdb, 0x4, 0x0, 0x0}},
419 {name: "inst=JMP/reg=BX/offset=2147483647", inst: JMP, dst: RegBX, dstOffset: 2147483647, exp: []byte{0xff, 0xa3, 0xff, 0xff, 0xff, 0x7f}},
420 {name: "inst=JMP/reg=BX/offset=-32768", inst: JMP, dst: RegBX, dstOffset: -32768, exp: []byte{0xff, 0xa3, 0x0, 0x80, 0xff, 0xff}},
421 {name: "inst=JMP/reg=SP/offset=0", inst: JMP, dst: RegSP, dstOffset: 0, exp: []byte{0xff, 0x24, 0x24}},
422 {name: "inst=JMP/reg=SP/offset=1", inst: JMP, dst: RegSP, dstOffset: 1, exp: []byte{0xff, 0x64, 0x24, 0x1}},
423 {name: "inst=JMP/reg=SP/offset=-1", inst: JMP, dst: RegSP, dstOffset: -1, exp: []byte{0xff, 0x64, 0x24, 0xff}},
424 {name: "inst=JMP/reg=SP/offset=1243", inst: JMP, dst: RegSP, dstOffset: 1243, exp: []byte{0xff, 0xa4, 0x24, 0xdb, 0x4, 0x0, 0x0}},
425 {name: "inst=JMP/reg=SP/offset=2147483647", inst: JMP, dst: RegSP, dstOffset: 2147483647, exp: []byte{0xff, 0xa4, 0x24, 0xff, 0xff, 0xff, 0x7f}},
426 {name: "inst=JMP/reg=SP/offset=-32768", inst: JMP, dst: RegSP, dstOffset: -32768, exp: []byte{0xff, 0xa4, 0x24, 0x0, 0x80, 0xff, 0xff}},
427 {name: "inst=JMP/reg=BP/offset=0", inst: JMP, dst: RegBP, dstOffset: 0, exp: []byte{0xff, 0x65, 0x0}},
428 {name: "inst=JMP/reg=BP/offset=1", inst: JMP, dst: RegBP, dstOffset: 1, exp: []byte{0xff, 0x65, 0x1}},
429 {name: "inst=JMP/reg=BP/offset=-1", inst: JMP, dst: RegBP, dstOffset: -1, exp: []byte{0xff, 0x65, 0xff}},
430 {name: "inst=JMP/reg=BP/offset=1243", inst: JMP, dst: RegBP, dstOffset: 1243, exp: []byte{0xff, 0xa5, 0xdb, 0x4, 0x0, 0x0}},
431 {name: "inst=JMP/reg=BP/offset=2147483647", inst: JMP, dst: RegBP, dstOffset: 2147483647, exp: []byte{0xff, 0xa5, 0xff, 0xff, 0xff, 0x7f}},
432 {name: "inst=JMP/reg=BP/offset=-32768", inst: JMP, dst: RegBP, dstOffset: -32768, exp: []byte{0xff, 0xa5, 0x0, 0x80, 0xff, 0xff}},
433 {name: "inst=JMP/reg=SI/offset=0", inst: JMP, dst: RegSI, dstOffset: 0, exp: []byte{0xff, 0x26}},
434 {name: "inst=JMP/reg=SI/offset=1", inst: JMP, dst: RegSI, dstOffset: 1, exp: []byte{0xff, 0x66, 0x1}},
435 {name: "inst=JMP/reg=SI/offset=-1", inst: JMP, dst: RegSI, dstOffset: -1, exp: []byte{0xff, 0x66, 0xff}},
436 {name: "inst=JMP/reg=SI/offset=1243", inst: JMP, dst: RegSI, dstOffset: 1243, exp: []byte{0xff, 0xa6, 0xdb, 0x4, 0x0, 0x0}},
437 {name: "inst=JMP/reg=SI/offset=2147483647", inst: JMP, dst: RegSI, dstOffset: 2147483647, exp: []byte{0xff, 0xa6, 0xff, 0xff, 0xff, 0x7f}},
438 {name: "inst=JMP/reg=SI/offset=-32768", inst: JMP, dst: RegSI, dstOffset: -32768, exp: []byte{0xff, 0xa6, 0x0, 0x80, 0xff, 0xff}},
439 {name: "inst=JMP/reg=DI/offset=0", inst: JMP, dst: RegDI, dstOffset: 0, exp: []byte{0xff, 0x27}},
440 {name: "inst=JMP/reg=DI/offset=1", inst: JMP, dst: RegDI, dstOffset: 1, exp: []byte{0xff, 0x67, 0x1}},
441 {name: "inst=JMP/reg=DI/offset=-1", inst: JMP, dst: RegDI, dstOffset: -1, exp: []byte{0xff, 0x67, 0xff}},
442 {name: "inst=JMP/reg=DI/offset=1243", inst: JMP, dst: RegDI, dstOffset: 1243, exp: []byte{0xff, 0xa7, 0xdb, 0x4, 0x0, 0x0}},
443 {name: "inst=JMP/reg=DI/offset=2147483647", inst: JMP, dst: RegDI, dstOffset: 2147483647, exp: []byte{0xff, 0xa7, 0xff, 0xff, 0xff, 0x7f}},
444 {name: "inst=JMP/reg=DI/offset=-32768", inst: JMP, dst: RegDI, dstOffset: -32768, exp: []byte{0xff, 0xa7, 0x0, 0x80, 0xff, 0xff}},
445 {name: "inst=JMP/reg=R8/offset=0", inst: JMP, dst: RegR8, dstOffset: 0, exp: []byte{0x41, 0xff, 0x20}},
446 {name: "inst=JMP/reg=R8/offset=1", inst: JMP, dst: RegR8, dstOffset: 1, exp: []byte{0x41, 0xff, 0x60, 0x1}},
447 {name: "inst=JMP/reg=R8/offset=-1", inst: JMP, dst: RegR8, dstOffset: -1, exp: []byte{0x41, 0xff, 0x60, 0xff}},
448 {name: "inst=JMP/reg=R8/offset=1243", inst: JMP, dst: RegR8, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa0, 0xdb, 0x4, 0x0, 0x0}},
449 {name: "inst=JMP/reg=R8/offset=2147483647", inst: JMP, dst: RegR8, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa0, 0xff, 0xff, 0xff, 0x7f}},
450 {name: "inst=JMP/reg=R8/offset=-32768", inst: JMP, dst: RegR8, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa0, 0x0, 0x80, 0xff, 0xff}},
451 {name: "inst=JMP/reg=R9/offset=0", inst: JMP, dst: RegR9, dstOffset: 0, exp: []byte{0x41, 0xff, 0x21}},
452 {name: "inst=JMP/reg=R9/offset=1", inst: JMP, dst: RegR9, dstOffset: 1, exp: []byte{0x41, 0xff, 0x61, 0x1}},
453 {name: "inst=JMP/reg=R9/offset=-1", inst: JMP, dst: RegR9, dstOffset: -1, exp: []byte{0x41, 0xff, 0x61, 0xff}},
454 {name: "inst=JMP/reg=R9/offset=1243", inst: JMP, dst: RegR9, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa1, 0xdb, 0x4, 0x0, 0x0}},
455 {name: "inst=JMP/reg=R9/offset=2147483647", inst: JMP, dst: RegR9, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa1, 0xff, 0xff, 0xff, 0x7f}},
456 {name: "inst=JMP/reg=R9/offset=-32768", inst: JMP, dst: RegR9, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa1, 0x0, 0x80, 0xff, 0xff}},
457 {name: "inst=JMP/reg=R13/offset=0", inst: JMP, dst: RegR13, dstOffset: 0, exp: []byte{0x41, 0xff, 0x65, 0x0}},
458 {name: "inst=JMP/reg=R13/offset=1", inst: JMP, dst: RegR13, dstOffset: 1, exp: []byte{0x41, 0xff, 0x65, 0x1}},
459 {name: "inst=JMP/reg=R13/offset=-1", inst: JMP, dst: RegR13, dstOffset: -1, exp: []byte{0x41, 0xff, 0x65, 0xff}},
460 {name: "inst=JMP/reg=R13/offset=1243", inst: JMP, dst: RegR13, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa5, 0xdb, 0x4, 0x0, 0x0}},
461 {name: "inst=JMP/reg=R13/offset=2147483647", inst: JMP, dst: RegR13, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa5, 0xff, 0xff, 0xff, 0x7f}},
462 {name: "inst=JMP/reg=R13/offset=-32768", inst: JMP, dst: RegR13, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa5, 0x0, 0x80, 0xff, 0xff}},
463 {name: "inst=JMP/reg=R14/offset=0", inst: JMP, dst: RegR14, dstOffset: 0, exp: []byte{0x41, 0xff, 0x26}},
464 {name: "inst=JMP/reg=R14/offset=1", inst: JMP, dst: RegR14, dstOffset: 1, exp: []byte{0x41, 0xff, 0x66, 0x1}},
465 {name: "inst=JMP/reg=R14/offset=-1", inst: JMP, dst: RegR14, dstOffset: -1, exp: []byte{0x41, 0xff, 0x66, 0xff}},
466 {name: "inst=JMP/reg=R14/offset=1243", inst: JMP, dst: RegR14, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa6, 0xdb, 0x4, 0x0, 0x0}},
467 {name: "inst=JMP/reg=R14/offset=2147483647", inst: JMP, dst: RegR14, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa6, 0xff, 0xff, 0xff, 0x7f}},
468 {name: "inst=JMP/reg=R14/offset=-32768", inst: JMP, dst: RegR14, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa6, 0x0, 0x80, 0xff, 0xff}},
469 {name: "inst=JMP/reg=R15/offset=0", inst: JMP, dst: RegR15, dstOffset: 0, exp: []byte{0x41, 0xff, 0x27}},
470 {name: "inst=JMP/reg=R15/offset=1", inst: JMP, dst: RegR15, dstOffset: 1, exp: []byte{0x41, 0xff, 0x67, 0x1}},
471 {name: "inst=JMP/reg=R15/offset=-1", inst: JMP, dst: RegR15, dstOffset: -1, exp: []byte{0x41, 0xff, 0x67, 0xff}},
472 {name: "inst=JMP/reg=R15/offset=1243", inst: JMP, dst: RegR15, dstOffset: 1243, exp: []byte{0x41, 0xff, 0xa7, 0xdb, 0x4, 0x0, 0x0}},
473 {name: "inst=JMP/reg=R15/offset=2147483647", inst: JMP, dst: RegR15, dstOffset: 2147483647, exp: []byte{0x41, 0xff, 0xa7, 0xff, 0xff, 0xff, 0x7f}},
474 {name: "inst=JMP/reg=R15/offset=-32768", inst: JMP, dst: RegR15, dstOffset: -32768, exp: []byte{0x41, 0xff, 0xa7, 0x0, 0x80, 0xff, 0xff}},
475 }
476
477 code := asm.CodeSegment{}
478 defer func() { require.NoError(t, code.Unmap()) }()
479
480 for _, tc := range tests {
481 tc := tc
482 a := NewAssembler()
483 buf := code.NextCodeSection()
484 err := a.encodeNoneToMemory(buf, &nodeImpl{
485 types: operandTypesNoneToMemory,
486 instruction: tc.inst, dstReg: tc.dst, dstConst: tc.dstOffset,
487 })
488 require.NoError(t, err, tc.name)
489 require.Equal(t, tc.exp, buf.Bytes(), tc.name)
490 }
491 }
492
493 func TestAssemblerImpl_EncodeRegisterToNone(t *testing.T) {
494 t.Run("error", func(t *testing.T) {
495 tests := []struct {
496 n *nodeImpl
497 expErr string
498 }{
499 {
500 n: &nodeImpl{instruction: ADDL, types: operandTypesRegisterToNone, srcReg: RegAX},
501 expErr: "ADDL is unsupported for RegisterToNone type",
502 },
503 }
504
505 for _, tc := range tests {
506 code := asm.CodeSegment{}
507 defer func() { require.NoError(t, code.Unmap()) }()
508
509 a := NewAssembler()
510 buf := code.NextCodeSection()
511 err := a.encodeRegisterToNone(buf, tc.n)
512 require.EqualError(t, err, tc.expErr, tc, tc.expErr)
513 }
514 })
515
516 tests := []struct {
517 name string
518 inst asm.Instruction
519 reg asm.Register
520 exp []byte
521 }{
522 {name: "DIVL/reg=AX/", reg: RegAX, inst: DIVL, exp: []byte{0xf7, 0xf0}},
523 {name: "DIVL/reg=BX/", reg: RegBX, inst: DIVL, exp: []byte{0xf7, 0xf3}},
524 {name: "DIVL/reg=SP/", reg: RegSP, inst: DIVL, exp: []byte{0xf7, 0xf4}},
525 {name: "DIVL/reg=BP/", reg: RegBP, inst: DIVL, exp: []byte{0xf7, 0xf5}},
526 {name: "DIVL/reg=SI/", reg: RegSI, inst: DIVL, exp: []byte{0xf7, 0xf6}},
527 {name: "DIVL/reg=DI/", reg: RegDI, inst: DIVL, exp: []byte{0xf7, 0xf7}},
528 {name: "DIVL/reg=R8/", reg: RegR8, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf0}},
529 {name: "DIVL/reg=R9/", reg: RegR9, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf1}},
530 {name: "DIVL/reg=R13/", reg: RegR13, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf5}},
531 {name: "DIVL/reg=R14/", reg: RegR14, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf6}},
532 {name: "DIVL/reg=R15/", reg: RegR15, inst: DIVL, exp: []byte{0x41, 0xf7, 0xf7}},
533 {name: "DIVQ/reg=AX/", reg: RegAX, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf0}},
534 {name: "DIVQ/reg=BX/", reg: RegBX, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf3}},
535 {name: "DIVQ/reg=SP/", reg: RegSP, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf4}},
536 {name: "DIVQ/reg=BP/", reg: RegBP, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf5}},
537 {name: "DIVQ/reg=SI/", reg: RegSI, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf6}},
538 {name: "DIVQ/reg=DI/", reg: RegDI, inst: DIVQ, exp: []byte{0x48, 0xf7, 0xf7}},
539 {name: "DIVQ/reg=R8/", reg: RegR8, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf0}},
540 {name: "DIVQ/reg=R9/", reg: RegR9, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf1}},
541 {name: "DIVQ/reg=R13/", reg: RegR13, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf5}},
542 {name: "DIVQ/reg=R14/", reg: RegR14, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf6}},
543 {name: "DIVQ/reg=R15/", reg: RegR15, inst: DIVQ, exp: []byte{0x49, 0xf7, 0xf7}},
544 {name: "IDIVL/reg=AX/", reg: RegAX, inst: IDIVL, exp: []byte{0xf7, 0xf8}},
545 {name: "IDIVL/reg=BX/", reg: RegBX, inst: IDIVL, exp: []byte{0xf7, 0xfb}},
546 {name: "IDIVL/reg=SP/", reg: RegSP, inst: IDIVL, exp: []byte{0xf7, 0xfc}},
547 {name: "IDIVL/reg=BP/", reg: RegBP, inst: IDIVL, exp: []byte{0xf7, 0xfd}},
548 {name: "IDIVL/reg=SI/", reg: RegSI, inst: IDIVL, exp: []byte{0xf7, 0xfe}},
549 {name: "IDIVL/reg=DI/", reg: RegDI, inst: IDIVL, exp: []byte{0xf7, 0xff}},
550 {name: "IDIVL/reg=R8/", reg: RegR8, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xf8}},
551 {name: "IDIVL/reg=R9/", reg: RegR9, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xf9}},
552 {name: "IDIVL/reg=R13/", reg: RegR13, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xfd}},
553 {name: "IDIVL/reg=R14/", reg: RegR14, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xfe}},
554 {name: "IDIVL/reg=R15/", reg: RegR15, inst: IDIVL, exp: []byte{0x41, 0xf7, 0xff}},
555 {name: "IDIVQ/reg=AX/", reg: RegAX, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xf8}},
556 {name: "IDIVQ/reg=BX/", reg: RegBX, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfb}},
557 {name: "IDIVQ/reg=SP/", reg: RegSP, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfc}},
558 {name: "IDIVQ/reg=BP/", reg: RegBP, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfd}},
559 {name: "IDIVQ/reg=SI/", reg: RegSI, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xfe}},
560 {name: "IDIVQ/reg=DI/", reg: RegDI, inst: IDIVQ, exp: []byte{0x48, 0xf7, 0xff}},
561 {name: "IDIVQ/reg=R8/", reg: RegR8, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xf8}},
562 {name: "IDIVQ/reg=R9/", reg: RegR9, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xf9}},
563 {name: "IDIVQ/reg=R13/", reg: RegR13, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xfd}},
564 {name: "IDIVQ/reg=R14/", reg: RegR14, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xfe}},
565 {name: "IDIVQ/reg=R15/", reg: RegR15, inst: IDIVQ, exp: []byte{0x49, 0xf7, 0xff}},
566 {name: "MULL/reg=AX/", reg: RegAX, inst: MULL, exp: []byte{0xf7, 0xe0}},
567 {name: "MULL/reg=BX/", reg: RegBX, inst: MULL, exp: []byte{0xf7, 0xe3}},
568 {name: "MULL/reg=SP/", reg: RegSP, inst: MULL, exp: []byte{0xf7, 0xe4}},
569 {name: "MULL/reg=BP/", reg: RegBP, inst: MULL, exp: []byte{0xf7, 0xe5}},
570 {name: "MULL/reg=SI/", reg: RegSI, inst: MULL, exp: []byte{0xf7, 0xe6}},
571 {name: "MULL/reg=DI/", reg: RegDI, inst: MULL, exp: []byte{0xf7, 0xe7}},
572 {name: "MULL/reg=R8/", reg: RegR8, inst: MULL, exp: []byte{0x41, 0xf7, 0xe0}},
573 {name: "MULL/reg=R9/", reg: RegR9, inst: MULL, exp: []byte{0x41, 0xf7, 0xe1}},
574 {name: "MULL/reg=R13/", reg: RegR13, inst: MULL, exp: []byte{0x41, 0xf7, 0xe5}},
575 {name: "MULL/reg=R14/", reg: RegR14, inst: MULL, exp: []byte{0x41, 0xf7, 0xe6}},
576 {name: "MULL/reg=R15/", reg: RegR15, inst: MULL, exp: []byte{0x41, 0xf7, 0xe7}},
577 {name: "MULQ/reg=AX/", reg: RegAX, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe0}},
578 {name: "MULQ/reg=BX/", reg: RegBX, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe3}},
579 {name: "MULQ/reg=SP/", reg: RegSP, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe4}},
580 {name: "MULQ/reg=BP/", reg: RegBP, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe5}},
581 {name: "MULQ/reg=SI/", reg: RegSI, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe6}},
582 {name: "MULQ/reg=DI/", reg: RegDI, inst: MULQ, exp: []byte{0x48, 0xf7, 0xe7}},
583 {name: "MULQ/reg=R8/", reg: RegR8, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe0}},
584 {name: "MULQ/reg=R9/", reg: RegR9, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe1}},
585 {name: "MULQ/reg=R13/", reg: RegR13, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe5}},
586 {name: "MULQ/reg=R14/", reg: RegR14, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe6}},
587 {name: "MULQ/reg=R15/", reg: RegR15, inst: MULQ, exp: []byte{0x49, 0xf7, 0xe7}},
588 }
589
590 code := asm.CodeSegment{}
591 defer func() { require.NoError(t, code.Unmap()) }()
592
593 for _, tc := range tests {
594 a := NewAssembler()
595 buf := code.NextCodeSection()
596 err := a.encodeRegisterToNone(buf, &nodeImpl{
597 instruction: tc.inst,
598 types: operandTypesRegisterToNone, srcReg: tc.reg,
599 })
600 require.NoError(t, err, tc.name)
601 require.Equal(t, tc.exp, buf.Bytes(), tc.name)
602 }
603 }
604
605 func TestAssemblerImpl_EncodeRegisterToRegister(t *testing.T) {
606 t.Run("error", func(t *testing.T) {
607 tests := []struct {
608 n *nodeImpl
609 expErr string
610 }{
611 {
612 n: &nodeImpl{instruction: JMP, types: operandTypesRegisterToRegister, srcReg: RegAX, dstReg: RegAX},
613 expErr: "JMP is unsupported for RegisterToRegister type",
614 },
615 }
616
617 for _, tc := range tests {
618 t.Run(tc.expErr, func(t *testing.T) {
619 code := asm.CodeSegment{}
620 defer func() { require.NoError(t, code.Unmap()) }()
621
622 a := NewAssembler()
623 buf := code.NextCodeSection()
624 err := a.encodeRegisterToRegister(buf, tc.n)
625 require.EqualError(t, err, tc.expErr)
626 })
627 }
628 })
629
630 tests := []struct {
631 name string
632 n *nodeImpl
633 exp []byte
634 }{
635 {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0xf3, 0x44, 0xf, 0x6f, 0xd3}},
636 {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX10, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x6f, 0xda}},
637 {name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0xf3, 0x45, 0xf, 0x6f, 0xfa}},
638 {name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x6f, 0xd3}},
639 {name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX10, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6f, 0xda}},
640 {name: "MOVDQA", n: &nodeImpl{instruction: MOVDQA, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0x66, 0x45, 0xf, 0x6f, 0xfa}},
641 {name: "PACKSSWB", n: &nodeImpl{instruction: PACKSSWB, srcReg: RegX10, dstReg: RegX15}, exp: []byte{0x66, 0x45, 0xf, 0x63, 0xfa}},
642 {name: "pmovmskb r15d, xmm10", n: &nodeImpl{instruction: PMOVMSKB, srcReg: RegX10, dstReg: RegR15}, exp: []byte{0x66, 0x45, 0xf, 0xd7, 0xfa}},
643 {name: "movmskps eax, xmm10", n: &nodeImpl{instruction: MOVMSKPS, srcReg: RegX10, dstReg: RegAX}, exp: []byte{0x41, 0xf, 0x50, 0xc2}},
644 {name: "movmskps r13d, xmm1", n: &nodeImpl{instruction: MOVMSKPS, srcReg: RegX1, dstReg: RegR13}, exp: []byte{0x44, 0xf, 0x50, 0xe9}},
645 {name: "movmskpd eax, xmm10", n: &nodeImpl{instruction: MOVMSKPD, srcReg: RegX10, dstReg: RegAX}, exp: []byte{0x66, 0x41, 0xf, 0x50, 0xc2}},
646 {name: "movmskpd r15d, xmm1", n: &nodeImpl{instruction: MOVMSKPD, srcReg: RegX1, dstReg: RegR15}, exp: []byte{0x66, 0x44, 0xf, 0x50, 0xf9}},
647 {name: "pand xmm15, xmm1", n: &nodeImpl{instruction: PAND, srcReg: RegX1, dstReg: RegX15}, exp: []byte{0x66, 0x44, 0xf, 0xdb, 0xf9}},
648 {name: "por xmm1, xmm15", n: &nodeImpl{instruction: POR, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xeb, 0xcf}},
649 {name: "pandn xmm13, xmm15", n: &nodeImpl{instruction: PANDN, srcReg: RegX15, dstReg: RegX13}, exp: []byte{0x66, 0x45, 0xf, 0xdf, 0xef}},
650 {name: "psrad xmm13, xmm15", n: &nodeImpl{instruction: PSRAD, srcReg: RegX15, dstReg: RegX13}, exp: []byte{0x66, 0x45, 0xf, 0xe2, 0xef}},
651 {name: "psraw xmm1, xmm1", n: &nodeImpl{instruction: PSRAW, srcReg: RegX1, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xe1, 0xc9}},
652 {name: "psrlq xmm14, xmm14", n: &nodeImpl{instruction: PSRLQ, srcReg: RegX14, dstReg: RegX14}, exp: []byte{0x66, 0x45, 0xf, 0xd3, 0xf6}},
653 {name: "psrld xmm3, xmm3", n: &nodeImpl{instruction: PSRLD, srcReg: RegX3, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0xd2, 0xdb}},
654 {name: "psrlw xmm15, xmm1", n: &nodeImpl{instruction: PSRLW, srcReg: RegX1, dstReg: RegX15}, exp: []byte{0x66, 0x44, 0xf, 0xd1, 0xf9}},
655 {name: "psllw xmm1, xmm15", n: &nodeImpl{instruction: PSLLW, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xf1, 0xcf}},
656 {name: "punpcklbw xmm1, xmm15", n: &nodeImpl{instruction: PUNPCKLBW, srcReg: RegX15, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x60, 0xcf}},
657 {name: "punpckhbw xmm11, xmm1", n: &nodeImpl{instruction: PUNPCKHBW, srcReg: RegX1, dstReg: RegX11}, exp: []byte{0x66, 0x44, 0xf, 0x68, 0xd9}},
658 {name: "pslld xmm11, xmm1", n: &nodeImpl{instruction: PSLLD, srcReg: RegX1, dstReg: RegX11}, exp: []byte{0x66, 0x44, 0xf, 0xf2, 0xd9}},
659 {name: "psllq xmm11, xmm15", n: &nodeImpl{instruction: PSLLQ, srcReg: RegX15, dstReg: RegX11}, exp: []byte{0x66, 0x45, 0xf, 0xf3, 0xdf}},
660 {
661 name: "cmpeqps xmm11, xmm15", n: &nodeImpl{instruction: CMPPS, srcReg: RegX15, dstReg: RegX11, arg: 0},
662 exp: []byte{0x45, 0xf, 0xc2, 0xdf, 0x0},
663 },
664 {
665 name: "cmpordps xmm1, xmm5", n: &nodeImpl{instruction: CMPPS, srcReg: RegX5, dstReg: RegX1, arg: 7},
666 exp: []byte{0xf, 0xc2, 0xcd, 0x7},
667 },
668 {name: "cmplepd xmm11, xmm15", n: &nodeImpl{instruction: CMPPD, srcReg: RegX15, dstReg: RegX11, arg: 2},
669 exp: []byte{0x66, 0x45, 0xf, 0xc2, 0xdf, 0x2}},
670 {
671 name: "cmpneqpd xmm1, xmm5", n: &nodeImpl{instruction: CMPPD, srcReg: RegX5, dstReg: RegX1, arg: 4},
672 exp: []byte{0x66, 0xf, 0xc2, 0xcd, 0x4},
673 },
674 {name: "pcmpgtq xmm10, xmm3", n: &nodeImpl{instruction: PCMPGTQ, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x37, 0xd3}},
675 {name: "pcmpgtd xmm10, xmm3", n: &nodeImpl{instruction: PCMPGTD, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x66, 0xd3}},
676 {name: "pminsd xmm10, xmm3", n: &nodeImpl{instruction: PMINSD, srcReg: RegX3, dstReg: RegX10}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x39, 0xd3}},
677 {name: "pmaxsd xmm1, xmm12", n: &nodeImpl{instruction: PMAXSD, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x3d, 0xcc}},
678 {name: "pmaxsw xmm1, xmm12", n: &nodeImpl{instruction: PMAXSW, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xee, 0xcc}},
679 {name: "pminsw xmm1, xmm12", n: &nodeImpl{instruction: PMINSW, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xea, 0xcc}},
680 {name: "pcmpgtb xmm1, xmm12", n: &nodeImpl{instruction: PCMPGTB, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x64, 0xcc}},
681 {name: "pminsb xmm1, xmm12", n: &nodeImpl{instruction: PMINSB, srcReg: RegX12, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x38, 0xcc}},
682 {name: "pmaxsb xmm1, xmm2", n: &nodeImpl{instruction: PMAXSB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3c, 0xca}},
683 {name: "pminud xmm1, xmm2", n: &nodeImpl{instruction: PMINUD, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3b, 0xca}},
684 {name: "pminuw xmm1, xmm2", n: &nodeImpl{instruction: PMINUW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3a, 0xca}},
685 {name: "pminub xmm1, xmm2", n: &nodeImpl{instruction: PMINUB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xda, 0xca}},
686 {name: "pmaxud xmm1, xmm2", n: &nodeImpl{instruction: PMAXUD, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3f, 0xca}},
687 {name: "pmaxuw xmm1, xmm2", n: &nodeImpl{instruction: PMAXUW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x38, 0x3e, 0xca}},
688 {name: "pmaxub xmm1, xmm2", n: &nodeImpl{instruction: PMAXUB, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0xde, 0xca}},
689 {name: "pcmpgtw xmm1, xmm2", n: &nodeImpl{instruction: PCMPGTW, srcReg: RegX2, dstReg: RegX1}, exp: []byte{0x66, 0xf, 0x65, 0xca}},
690 {name: "pmullw xmm13, xmm1", n: &nodeImpl{instruction: PMULLW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd5, 0xe9}},
691 {name: "pmulld xmm1, xmm11", n: &nodeImpl{instruction: PMULLD, srcReg: RegX11, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x40, 0xcb}},
692 {name: "pmuludq xmm13, xmm1", n: &nodeImpl{instruction: PMULUDQ, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xf4, 0xe9}},
693 {name: "psubsb xmm13, xmm1", n: &nodeImpl{instruction: PSUBSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe8, 0xe9}},
694 {name: "psubsw xmm13, xmm1", n: &nodeImpl{instruction: PSUBSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe9, 0xe9}},
695 {name: "psubusb xmm13, xmm1", n: &nodeImpl{instruction: PSUBUSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd8, 0xe9}},
696 {name: "psubusw xmm13, xmm1", n: &nodeImpl{instruction: PSUBUSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xd9, 0xe9}},
697 {name: "paddsw xmm13, xmm1", n: &nodeImpl{instruction: PADDSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xed, 0xe9}},
698 {name: "paddsb xmm13, xmm1", n: &nodeImpl{instruction: PADDSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xec, 0xe9}},
699 {name: "paddusw xmm13, xmm1", n: &nodeImpl{instruction: PADDUSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xdd, 0xe9}},
700 {name: "pavgb xmm13, xmm1", n: &nodeImpl{instruction: PAVGB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe0, 0xe9}},
701 {name: "pavgw xmm13, xmm1", n: &nodeImpl{instruction: PAVGW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe3, 0xe9}},
702 {name: "pabsb xmm13, xmm1", n: &nodeImpl{instruction: PABSB, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1c, 0xe9}},
703 {name: "pabsw xmm13, xmm1", n: &nodeImpl{instruction: PABSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1d, 0xe9}},
704 {name: "pabsd xmm13, xmm1", n: &nodeImpl{instruction: PABSD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x1e, 0xe9}},
705 {name: "blendvpd xmm13, xmm1", n: &nodeImpl{instruction: BLENDVPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x15, 0xe9}},
706 {name: "maxpd xmm13, xmm1", n: &nodeImpl{instruction: MAXPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5f, 0xe9}},
707 {name: "maxps xmm13, xmm1", n: &nodeImpl{instruction: MAXPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5f, 0xe9}},
708 {name: "minpd xmm13, xmm1", n: &nodeImpl{instruction: MINPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5d, 0xe9}},
709 {name: "minps xmm13, xmm1", n: &nodeImpl{instruction: MINPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5d, 0xe9}},
710 {name: "andnpd xmm13, xmm1", n: &nodeImpl{instruction: ANDNPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x55, 0xe9}},
711 {name: "andnps xmm13, xmm1", n: &nodeImpl{instruction: ANDNPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x55, 0xe9}},
712 {name: "mulps xmm13, xmm1", n: &nodeImpl{instruction: MULPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x59, 0xe9}},
713 {name: "mulpd xmm13, xmm1", n: &nodeImpl{instruction: MULPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x59, 0xe9}},
714 {name: "divps xmm13, xmm1", n: &nodeImpl{instruction: DIVPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x5e, 0xe9}},
715 {name: "divpd xmm13, xmm1", n: &nodeImpl{instruction: DIVPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x5e, 0xe9}},
716 {name: "sqrtps xmm13, xmm1", n: &nodeImpl{instruction: SQRTPS, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x44, 0xf, 0x51, 0xe9}},
717 {name: "sqrtpd xmm13, xmm1", n: &nodeImpl{instruction: SQRTPD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x51, 0xe9}},
718 {name: "roundps xmm13, xmm1, 0", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x0}},
719 {name: "roundps xmm13, xmm1, 1", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x1}},
720 {name: "roundps xmm13, xmm1, 3", n: &nodeImpl{instruction: ROUNDPS, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x8, 0xe9, 0x3}},
721 {name: "roundpd xmm13, xmm1, 0", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x0}},
722 {name: "roundpd xmm13, xmm1, 1", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x1}},
723 {name: "roundpd xmm13, xmm1, 3", n: &nodeImpl{instruction: ROUNDPD, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x9, 0xe9, 0x3}},
724 {name: "palignr xmm13, xmm1, 3", n: &nodeImpl{instruction: PALIGNR, srcReg: RegX1, dstReg: RegX13, arg: 3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xf, 0xe9, 0x3}},
725 {name: "punpcklwd xmm13, xmm1", n: &nodeImpl{instruction: PUNPCKLWD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x61, 0xe9}},
726 {name: "punpckhwd xmm13, xmm1", n: &nodeImpl{instruction: PUNPCKHWD, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x69, 0xe9}},
727 {name: "pmulhuw xmm13, xmm1", n: &nodeImpl{instruction: PMULHUW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0xe4, 0xe9}},
728 {name: "pmuldq xmm13, xmm1", n: &nodeImpl{instruction: PMULDQ, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x28, 0xe9}},
729 {name: "pmulhrsw xmm13, xmm1", n: &nodeImpl{instruction: PMULHRSW, srcReg: RegX1, dstReg: RegX13}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0xb, 0xe9}},
730 {name: "pmovsxbw xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0xea}},
731 {name: "pmovsxwd xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0xea}},
732 {name: "pmovsxdq xmm5, xmm10", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0xea}},
733 {name: "pmovzxbw xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0xea}},
734 {name: "pmovzxwd xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0xea}},
735 {name: "pmovzxdq xmm5, xmm10", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegX10, dstReg: RegX5}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0xea}},
736 {name: "pmulhw xmm2, xmm1", n: &nodeImpl{instruction: PMULHW, srcReg: RegX1, dstReg: RegX2}, exp: []byte{0x66, 0xf, 0xe5, 0xd1}},
737 {name: "cmpltps xmm1, xmm14", n: &nodeImpl{instruction: CMPEQPS, srcReg: RegX14, dstReg: RegX1, arg: 1}, exp: []byte{0x41, 0xf, 0xc2, 0xce, 0x1}},
738 {name: "cmpunordpd xmm1, xmm14", n: &nodeImpl{instruction: CMPEQPD, srcReg: RegX14, dstReg: RegX1, arg: 3}, exp: []byte{0x66, 0x41, 0xf, 0xc2, 0xce, 0x3}},
739 {name: "cvttps2dq xmm1, xmm14", n: &nodeImpl{instruction: CVTTPS2DQ, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0xf3, 0x41, 0xf, 0x5b, 0xce}},
740 {name: "cvtdq2ps xmm1, xmm14", n: &nodeImpl{instruction: CVTDQ2PS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x5b, 0xce}},
741 {name: "movupd xmm1, xmm14", n: &nodeImpl{instruction: MOVUPD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x10, 0xce}},
742 {name: "shufps xmm1, xmm14, 5", n: &nodeImpl{instruction: SHUFPS, srcReg: RegX14, dstReg: RegX1, arg: 5}, exp: []byte{0x41, 0xf, 0xc6, 0xce, 0x5}},
743 {name: "pmaddwd xmm1, xmm14", n: &nodeImpl{instruction: PMADDWD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xf5, 0xce}},
744 {name: "cvtdq2pd xmm1, xmm14", n: &nodeImpl{instruction: CVTDQ2PD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0xf3, 0x41, 0xf, 0xe6, 0xce}},
745 {name: "unpcklps xmm1, xmm14", n: &nodeImpl{instruction: UNPCKLPS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x14, 0xce}},
746 {name: "packuswb xmm1, xmm14", n: &nodeImpl{instruction: PACKUSWB, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x67, 0xce}},
747 {name: "packssdw xmm1, xmm14", n: &nodeImpl{instruction: PACKSSDW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x6b, 0xce}},
748 {name: "packusdw xmm1, xmm14", n: &nodeImpl{instruction: PACKUSDW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x2b, 0xce}},
749 {name: "cvtps2pd xmm1, xmm14", n: &nodeImpl{instruction: CVTPS2PD, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x41, 0xf, 0x5a, 0xce}},
750 {name: "cvtpd2ps xmm1, xmm14", n: &nodeImpl{instruction: CVTPD2PS, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x5a, 0xce}},
751 {name: "pmaddubsw xmm1, xmm14", n: &nodeImpl{instruction: PMADDUBSW, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x4, 0xce}},
752 {name: "cvttpd2dq xmm1, xmm14", n: &nodeImpl{instruction: CVTTPD2DQ, srcReg: RegX14, dstReg: RegX1}, exp: []byte{0x66, 0x41, 0xf, 0xe6, 0xce}},
753 {name: "PADDB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfc, 0xc0}},
754 {name: "PADDB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfc, 0xc0}},
755 {name: "PADDB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfc, 0xc0}},
756 {name: "PADDB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfc, 0xc0}},
757 {name: "PADDW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfd, 0xc0}},
758 {name: "PADDW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfd, 0xc0}},
759 {name: "PADDW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfd, 0xc0}},
760 {name: "PADDW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfd, 0xc0}},
761 {name: "PADDD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfe, 0xc0}},
762 {name: "PADDD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfe, 0xc0}},
763 {name: "PADDD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfe, 0xc0}},
764 {name: "PADDD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfe, 0xc0}},
765 {name: "PADDQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xd4, 0xc0}},
766 {name: "PADDQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xd4, 0xc0}},
767 {name: "PADDQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xd4, 0xc0}},
768 {name: "PADDQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xd4, 0xc0}},
769 {name: "ADDPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x58, 0xc0}},
770 {name: "ADDPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x58, 0xc0}},
771 {name: "ADDPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x58, 0xc0}},
772 {name: "ADDPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x58, 0xc0}},
773 {name: "ADDPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x58, 0xc0}},
774 {name: "ADDPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x58, 0xc0}},
775 {name: "ADDPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x58, 0xc0}},
776 {name: "ADDPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x58, 0xc0}},
777 {name: "PSUBB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xf8, 0xc0}},
778 {name: "PSUBB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xf8, 0xc0}},
779 {name: "PSUBB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xf8, 0xc0}},
780 {name: "PSUBB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xf8, 0xc0}},
781 {name: "PSUBW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xf9, 0xc0}},
782 {name: "PSUBW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xf9, 0xc0}},
783 {name: "PSUBW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xf9, 0xc0}},
784 {name: "PSUBW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xf9, 0xc0}},
785 {name: "PSUBL/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfa, 0xc0}},
786 {name: "PSUBL/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfa, 0xc0}},
787 {name: "PSUBL/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfa, 0xc0}},
788 {name: "PSUBL/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfa, 0xc0}},
789 {name: "PSUBQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xfb, 0xc0}},
790 {name: "PSUBQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xfb, 0xc0}},
791 {name: "PSUBQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xfb, 0xc0}},
792 {name: "PSUBQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSUBQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xfb, 0xc0}},
793 {name: "SUBPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x5c, 0xc0}},
794 {name: "SUBPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x5c, 0xc0}},
795 {name: "SUBPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x5c, 0xc0}},
796 {name: "SUBPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x5c, 0xc0}},
797 {name: "SUBPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x5c, 0xc0}},
798 {name: "SUBPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x5c, 0xc0}},
799 {name: "SUBPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x5c, 0xc0}},
800 {name: "SUBPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x5c, 0xc0}},
801 {name: "PINSRQ/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
802 {name: "PINSRQ/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
803 {name: "PINSRQ/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
804 {name: "PINSRQ/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
805 {name: "PINSRQ/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
806 {name: "PINSRQ/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
807 {name: "PINSRQ/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
808 {name: "PINSRQ/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
809 {name: "PINSRD/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
810 {name: "PINSRD/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
811 {name: "PINSRD/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
812 {name: "PINSRD/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x22, 0xc0, 0x1}},
813 {name: "PINSRD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
814 {name: "PINSRD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
815 {name: "PINSRD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
816 {name: "PINSRD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x22, 0xc0, 0x0}},
817 {name: "PINSRW/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0xc4, 0xc0, 0x1}},
818 {name: "PINSRW/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xc0, 0x1}},
819 {name: "PINSRW/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0xc4, 0xc0, 0x1}},
820 {name: "PINSRW/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0xc4, 0xc0, 0x1}},
821 {name: "PINSRW/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xc4, 0xc0, 0x0}},
822 {name: "PINSRW/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xc0, 0x0}},
823 {name: "PINSRW/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xc4, 0xc0, 0x0}},
824 {name: "PINSRW/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xc4, 0xc0, 0x0}},
825 {name: "PINSRB/src=AX/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0xc0, 0x1}},
826 {name: "PINSRB/src=AX/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xc0, 0x1}},
827 {name: "PINSRB/src=R8/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x20, 0xc0, 0x1}},
828 {name: "PINSRB/src=R8/dst=X8/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x20, 0xc0, 0x1}},
829 {name: "PINSRB/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0xc0, 0x0}},
830 {name: "PINSRB/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xc0, 0x0}},
831 {name: "PINSRB/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x20, 0xc0, 0x0}},
832 {name: "PINSRB/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x20, 0xc0, 0x0}},
833 {name: "ADDL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x1, 0xc0}},
834 {name: "ADDL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x1, 0xc0}},
835 {name: "ADDL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x1, 0xc0}},
836 {name: "ADDL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ADDL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x1, 0xc0}},
837 {name: "ADDQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x1, 0xc0}},
838 {name: "ADDQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x1, 0xc0}},
839 {name: "ADDQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x1, 0xc0}},
840 {name: "ADDQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ADDQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x1, 0xc0}},
841 {name: "ADDSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x58, 0xc0}},
842 {name: "ADDSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x58, 0xc0}},
843 {name: "ADDSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x58, 0xc0}},
844 {name: "ADDSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x58, 0xc0}},
845 {name: "ADDSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x58, 0xc0}},
846 {name: "ADDSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x58, 0xc0}},
847 {name: "ADDSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x58, 0xc0}},
848 {name: "ADDSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ADDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x58, 0xc0}},
849 {name: "ANDL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x21, 0xc0}},
850 {name: "ANDL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x21, 0xc0}},
851 {name: "ANDL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x21, 0xc0}},
852 {name: "ANDL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ANDL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x21, 0xc0}},
853 {name: "ANDPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x54, 0xc0}},
854 {name: "ANDPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x54, 0xc0}},
855 {name: "ANDPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x54, 0xc0}},
856 {name: "ANDPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x54, 0xc0}},
857 {name: "ANDPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x54, 0xc0}},
858 {name: "ANDPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x54, 0xc0}},
859 {name: "ANDPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x54, 0xc0}},
860 {name: "ANDPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ANDPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x54, 0xc0}},
861 {name: "ANDQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x21, 0xc0}},
862 {name: "ANDQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x21, 0xc0}},
863 {name: "ANDQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x21, 0xc0}},
864 {name: "ANDQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ANDQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x21, 0xc0}},
865 {name: "BSRL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbd, 0xc0}},
866 {name: "BSRL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbd, 0xc0}},
867 {name: "BSRL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbd, 0xc0}},
868 {name: "BSRL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: BSRL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbd, 0xc0}},
869 {name: "BSRQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbd, 0xc0}},
870 {name: "BSRQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbd, 0xc0}},
871 {name: "BSRQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbd, 0xc0}},
872 {name: "BSRQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: BSRQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbd, 0xc0}},
873 {name: "CMOVQCS/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0x42, 0xc0}},
874 {name: "CMOVQCS/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0x42, 0xc0}},
875 {name: "CMOVQCS/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0x42, 0xc0}},
876 {name: "CMOVQCS/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMOVQCS, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0x42, 0xc0}},
877 {name: "CMPL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x39, 0xc0}},
878 {name: "CMPL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0x39, 0xc0}},
879 {name: "CMPL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0x39, 0xc0}},
880 {name: "CMPL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMPL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x39, 0xc0}},
881 {name: "CMPQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x39, 0xc0}},
882 {name: "CMPQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0x39, 0xc0}},
883 {name: "CMPQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0x39, 0xc0}},
884 {name: "CMPQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: CMPQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x39, 0xc0}},
885 {name: "COMISD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x2f, 0xc0}},
886 {name: "COMISD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x2f, 0xc0}},
887 {name: "COMISD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x2f, 0xc0}},
888 {name: "COMISD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: COMISD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x2f, 0xc0}},
889 {name: "COMISS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x2f, 0xc0}},
890 {name: "COMISS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x2f, 0xc0}},
891 {name: "COMISS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x2f, 0xc0}},
892 {name: "COMISS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: COMISS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x2f, 0xc0}},
893 {name: "CVTSD2SS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5a, 0xc0}},
894 {name: "CVTSD2SS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5a, 0xc0}},
895 {name: "CVTSD2SS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5a, 0xc0}},
896 {name: "CVTSD2SS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSD2SS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5a, 0xc0}},
897 {name: "CVTSL2SD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x2a, 0xc0}},
898 {name: "CVTSL2SD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x2a, 0xc0}},
899 {name: "CVTSL2SD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x2a, 0xc0}},
900 {name: "CVTSL2SD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x2a, 0xc0}},
901 {name: "CVTSL2SS/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x2a, 0xc0}},
902 {name: "CVTSL2SS/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x2a, 0xc0}},
903 {name: "CVTSL2SS/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x2a, 0xc0}},
904 {name: "CVTSL2SS/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSL2SS, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x2a, 0xc0}},
905 {name: "CVTSQ2SD/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x48, 0xf, 0x2a, 0xc0}},
906 {name: "CVTSQ2SD/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x4c, 0xf, 0x2a, 0xc0}},
907 {name: "CVTSQ2SD/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x49, 0xf, 0x2a, 0xc0}},
908 {name: "CVTSQ2SD/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SD, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x4d, 0xf, 0x2a, 0xc0}},
909 {name: "CVTSQ2SS/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0x2a, 0xc0}},
910 {name: "CVTSQ2SS/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0x2a, 0xc0}},
911 {name: "CVTSQ2SS/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0x2a, 0xc0}},
912 {name: "CVTSQ2SS/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSQ2SS, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0x2a, 0xc0}},
913 {name: "CVTSS2SD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5a, 0xc0}},
914 {name: "CVTSS2SD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5a, 0xc0}},
915 {name: "CVTSS2SD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5a, 0xc0}},
916 {name: "CVTSS2SD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: CVTSS2SD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5a, 0xc0}},
917 {name: "CVTTSD2SL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x2c, 0xc0}},
918 {name: "CVTTSD2SL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x2c, 0xc0}},
919 {name: "CVTTSD2SL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x2c, 0xc0}},
920 {name: "CVTTSD2SL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x2c, 0xc0}},
921 {name: "CVTTSD2SQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x48, 0xf, 0x2c, 0xc0}},
922 {name: "CVTTSD2SQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x4c, 0xf, 0x2c, 0xc0}},
923 {name: "CVTTSD2SQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf2, 0x49, 0xf, 0x2c, 0xc0}},
924 {name: "CVTTSD2SQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSD2SQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf2, 0x4d, 0xf, 0x2c, 0xc0}},
925 {name: "CVTTSS2SL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x2c, 0xc0}},
926 {name: "CVTTSS2SL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x2c, 0xc0}},
927 {name: "CVTTSS2SL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x2c, 0xc0}},
928 {name: "CVTTSS2SL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x2c, 0xc0}},
929 {name: "CVTTSS2SQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0x2c, 0xc0}},
930 {name: "CVTTSS2SQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0x2c, 0xc0}},
931 {name: "CVTTSS2SQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0x2c, 0xc0}},
932 {name: "CVTTSS2SQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: CVTTSS2SQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0x2c, 0xc0}},
933 {name: "DIVSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5e, 0xc0}},
934 {name: "DIVSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5e, 0xc0}},
935 {name: "DIVSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5e, 0xc0}},
936 {name: "DIVSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5e, 0xc0}},
937 {name: "DIVSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5e, 0xc0}},
938 {name: "DIVSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5e, 0xc0}},
939 {name: "DIVSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5e, 0xc0}},
940 {name: "DIVSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: DIVSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5e, 0xc0}},
941 {name: "LZCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xbd, 0xc0}},
942 {name: "LZCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xbd, 0xc0}},
943 {name: "LZCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xbd, 0xc0}},
944 {name: "LZCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xbd, 0xc0}},
945 {name: "LZCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xbd, 0xc0}},
946 {name: "LZCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xbd, 0xc0}},
947 {name: "LZCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xbd, 0xc0}},
948 {name: "LZCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: LZCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xbd, 0xc0}},
949 {name: "MAXSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5f, 0xc0}},
950 {name: "MAXSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5f, 0xc0}},
951 {name: "MAXSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5f, 0xc0}},
952 {name: "MAXSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5f, 0xc0}},
953 {name: "MINSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5d, 0xc0}},
954 {name: "MINSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5d, 0xc0}},
955 {name: "MINSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5d, 0xc0}},
956 {name: "MINSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MINSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5d, 0xc0}},
957 {name: "MAXSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5f, 0xc0}},
958 {name: "MAXSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5f, 0xc0}},
959 {name: "MAXSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5f, 0xc0}},
960 {name: "MAXSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MAXSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5f, 0xc0}},
961 {name: "MINSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5d, 0xc0}},
962 {name: "MINSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5d, 0xc0}},
963 {name: "MINSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5d, 0xc0}},
964 {name: "MINSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MINSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5d, 0xc0}},
965 {name: "MOVBLSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbe, 0xc0}},
966 {name: "MOVBLSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbe, 0xc0}},
967 {name: "MOVBLSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbe, 0xc0}},
968 {name: "MOVBLSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbe, 0xc0}},
969 {name: "MOVWLZX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xb7, 0xc0}},
970 {name: "MOVWLZX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xb7, 0xc0}},
971 {name: "MOVWLZX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xb7, 0xc0}},
972 {name: "MOVWLZX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xb7, 0xc0}},
973 {name: "MOVBLZX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xb6, 0xc0}},
974 {name: "MOVBLZX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xb6, 0xc0}},
975 {name: "MOVBLZX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xb6, 0xc0}},
976 {name: "MOVBLZX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xb6, 0xc0}},
977 {name: "MOVBQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbe, 0xc0}},
978 {name: "MOVBQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbe, 0xc0}},
979 {name: "MOVBQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbe, 0xc0}},
980 {name: "MOVBQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbe, 0xc0}},
981 {name: "MOVLQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x63, 0xc0}},
982 {name: "MOVLQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0x63, 0xc0}},
983 {name: "MOVLQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0x63, 0xc0}},
984 {name: "MOVLQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x63, 0xc0}},
985 {name: "MOVL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x89, 0xc0}},
986 {name: "MOVL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x89, 0xc0}},
987 {name: "MOVL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x89, 0xc0}},
988 {name: "MOVL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x89, 0xc0}},
989 {name: "MOVL/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x6e, 0xc0}},
990 {name: "MOVL/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x6e, 0xc0}},
991 {name: "MOVL/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0xc0}},
992 {name: "MOVL/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x6e, 0xc0}},
993 {name: "MOVL/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0xf, 0x7e, 0xc0}},
994 {name: "MOVL/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x7e, 0xc0}},
995 {name: "MOVL/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x7e, 0xc0}},
996 {name: "MOVL/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVL, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x7e, 0xc0}},
997 {name: "MOVQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x89, 0xc0}},
998 {name: "MOVQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x89, 0xc0}},
999 {name: "MOVQ/src=AX/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x6e, 0xc0}},
1000 {name: "MOVQ/src=AX/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x6e, 0xc0}},
1001 {name: "MOVQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x89, 0xc0}},
1002 {name: "MOVQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x89, 0xc0}},
1003 {name: "MOVQ/src=R8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x6e, 0xc0}},
1004 {name: "MOVQ/src=R8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegR8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x6e, 0xc0}},
1005 {name: "MOVQ/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x48, 0xf, 0x7e, 0xc0}},
1006 {name: "MOVQ/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x49, 0xf, 0x7e, 0xc0}},
1007 {name: "MOVQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x7e, 0xc0}},
1008 {name: "MOVQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x7e, 0xc0}},
1009 {name: "MOVQ/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x4c, 0xf, 0x7e, 0xc0}},
1010 {name: "MOVQ/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x4d, 0xf, 0x7e, 0xc0}},
1011 {name: "MOVQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0xc0}},
1012 {name: "MOVQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x7e, 0xc0}},
1013 {name: "MOVWLSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf, 0xbf, 0xc0}},
1014 {name: "MOVWLSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x44, 0xf, 0xbf, 0xc0}},
1015 {name: "MOVWLSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x41, 0xf, 0xbf, 0xc0}},
1016 {name: "MOVWLSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0xf, 0xbf, 0xc0}},
1017 {name: "MOVWQSX/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xbf, 0xc0}},
1018 {name: "MOVWQSX/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4c, 0xf, 0xbf, 0xc0}},
1019 {name: "MOVWQSX/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xbf, 0xc0}},
1020 {name: "MOVWQSX/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xbf, 0xc0}},
1021 {name: "MULSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x59, 0xc0}},
1022 {name: "MULSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x59, 0xc0}},
1023 {name: "MULSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x59, 0xc0}},
1024 {name: "MULSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MULSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x59, 0xc0}},
1025 {name: "MULSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x59, 0xc0}},
1026 {name: "MULSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x59, 0xc0}},
1027 {name: "MULSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x59, 0xc0}},
1028 {name: "MULSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MULSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x59, 0xc0}},
1029 {name: "IMULQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0xf, 0xaf, 0xc0}},
1030 {name: "IMULQ/src=DX/dst=AX/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegDX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xf, 0xaf, 0xc2}},
1031 {name: "IMULQ/src=R10/dst=CX/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegR10, dstReg: RegCX, arg: 0x0}, exp: []byte{0x49, 0xf, 0xaf, 0xca}},
1032 {name: "IMULQ/src=CX/dst=DI/arg=0", n: &nodeImpl{instruction: IMULQ, srcReg: RegCX, dstReg: RegDI, arg: 0x0}, exp: []byte{0x48, 0xf, 0xaf, 0xf9}},
1033 {name: "ORL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x9, 0xc0}},
1034 {name: "ORL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x9, 0xc0}},
1035 {name: "ORL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x9, 0xc0}},
1036 {name: "ORL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ORL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x9, 0xc0}},
1037 {name: "ORPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x56, 0xc0}},
1038 {name: "ORPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x56, 0xc0}},
1039 {name: "ORPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x56, 0xc0}},
1040 {name: "ORPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ORPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x56, 0xc0}},
1041 {name: "ORPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x56, 0xc0}},
1042 {name: "ORPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x56, 0xc0}},
1043 {name: "ORPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x56, 0xc0}},
1044 {name: "ORPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ORPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x56, 0xc0}},
1045 {name: "ORQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x9, 0xc0}},
1046 {name: "ORQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x9, 0xc0}},
1047 {name: "ORQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x9, 0xc0}},
1048 {name: "ORQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: ORQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x9, 0xc0}},
1049 {name: "POPCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xb8, 0xc0}},
1050 {name: "POPCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xb8, 0xc0}},
1051 {name: "POPCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xb8, 0xc0}},
1052 {name: "POPCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xb8, 0xc0}},
1053 {name: "POPCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xb8, 0xc0}},
1054 {name: "POPCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xb8, 0xc0}},
1055 {name: "POPCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xb8, 0xc0}},
1056 {name: "POPCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: POPCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xb8, 0xc0}},
1057 {name: "ROLL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xc0}},
1058 {name: "ROLL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: ROLL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xc0}},
1059 {name: "ROLQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xc0}},
1060 {name: "ROLQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: ROLQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xc0}},
1061 {name: "RORL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xc8}},
1062 {name: "RORL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: RORL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xc8}},
1063 {name: "RORQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xc8}},
1064 {name: "RORQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: RORQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xc8}},
1065 {name: "ROUNDSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x0}},
1066 {name: "ROUNDSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x0}},
1067 {name: "ROUNDSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x0}},
1068 {name: "ROUNDSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x0}},
1069 {name: "ROUNDSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x0}},
1070 {name: "ROUNDSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x0}},
1071 {name: "ROUNDSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x0}},
1072 {name: "ROUNDSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x0}},
1073 {name: "ROUNDSD/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x1}},
1074 {name: "ROUNDSD/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x1}},
1075 {name: "ROUNDSD/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x1}},
1076 {name: "ROUNDSD/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x1}},
1077 {name: "ROUNDSS/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x1}},
1078 {name: "ROUNDSS/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x1}},
1079 {name: "ROUNDSS/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x1}},
1080 {name: "ROUNDSS/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x1}},
1081 {name: "ROUNDSD/src=X0/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x2}},
1082 {name: "ROUNDSD/src=X0/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x2}},
1083 {name: "ROUNDSD/src=X8/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x2}},
1084 {name: "ROUNDSD/src=X8/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x2}},
1085 {name: "ROUNDSS/src=X0/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x2}},
1086 {name: "ROUNDSS/src=X0/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x2}},
1087 {name: "ROUNDSS/src=X8/dst=X0/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x2}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x2}},
1088 {name: "ROUNDSS/src=X8/dst=X8/arg=2", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x2}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x2}},
1089 {name: "ROUNDSD/src=X0/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x3}},
1090 {name: "ROUNDSD/src=X0/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x3}},
1091 {name: "ROUNDSD/src=X8/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x3}},
1092 {name: "ROUNDSD/src=X8/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x3}},
1093 {name: "ROUNDSS/src=X0/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x3}},
1094 {name: "ROUNDSS/src=X0/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x3}},
1095 {name: "ROUNDSS/src=X8/dst=X0/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x3}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x3}},
1096 {name: "ROUNDSS/src=X8/dst=X8/arg=3", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x3}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x3}},
1097 {name: "ROUNDSD/src=X0/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0xf, 0x3a, 0xb, 0xc0, 0x4}},
1098 {name: "ROUNDSD/src=X0/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX0, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xb, 0xc0, 0x4}},
1099 {name: "ROUNDSD/src=X8/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xb, 0xc0, 0x4}},
1100 {name: "ROUNDSD/src=X8/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSD, srcReg: RegX8, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xb, 0xc0, 0x4}},
1101 {name: "ROUNDSS/src=X0/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0xf, 0x3a, 0xa, 0xc0, 0x4}},
1102 {name: "ROUNDSS/src=X0/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX0, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0xa, 0xc0, 0x4}},
1103 {name: "ROUNDSS/src=X8/dst=X0/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX0, arg: 0x4}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0xa, 0xc0, 0x4}},
1104 {name: "ROUNDSS/src=X8/dst=X8/arg=4", n: &nodeImpl{instruction: ROUNDSS, srcReg: RegX8, dstReg: RegX8, arg: 0x4}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0xa, 0xc0, 0x4}},
1105 {name: "SARL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xf8}},
1106 {name: "SARL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SARL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xf8}},
1107 {name: "SARQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xf8}},
1108 {name: "SARQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SARQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xf8}},
1109 {name: "SHLL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xe0}},
1110 {name: "SHLL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHLL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xe0}},
1111 {name: "SHLQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xe0}},
1112 {name: "SHLQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHLQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xe0}},
1113 {name: "SHRL/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xd3, 0xe8}},
1114 {name: "SHRL/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHRL, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0xd3, 0xe8}},
1115 {name: "SHRQ/src=CX/dst=AX/arg=0", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0xd3, 0xe8}},
1116 {name: "SHRQ/src=CX/dst=R8/arg=0", n: &nodeImpl{instruction: SHRQ, srcReg: RegCX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0xd3, 0xe8}},
1117 {name: "SQRTSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x51, 0xc0}},
1118 {name: "SQRTSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x51, 0xc0}},
1119 {name: "SQRTSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x51, 0xc0}},
1120 {name: "SQRTSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x51, 0xc0}},
1121 {name: "SQRTSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x51, 0xc0}},
1122 {name: "SQRTSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x51, 0xc0}},
1123 {name: "SQRTSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x51, 0xc0}},
1124 {name: "SQRTSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SQRTSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x51, 0xc0}},
1125 {name: "SUBL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x29, 0xc0}},
1126 {name: "SUBL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x29, 0xc0}},
1127 {name: "SUBL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x29, 0xc0}},
1128 {name: "SUBL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: SUBL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x29, 0xc0}},
1129 {name: "SUBQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x29, 0xc0}},
1130 {name: "SUBQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x29, 0xc0}},
1131 {name: "SUBQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x29, 0xc0}},
1132 {name: "SUBQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: SUBQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x29, 0xc0}},
1133 {name: "SUBSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x5c, 0xc0}},
1134 {name: "SUBSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x5c, 0xc0}},
1135 {name: "SUBSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0xc0}},
1136 {name: "SUBSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x5c, 0xc0}},
1137 {name: "SUBSS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0xf, 0x5c, 0xc0}},
1138 {name: "SUBSS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0x5c, 0xc0}},
1139 {name: "SUBSS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0xc0}},
1140 {name: "SUBSS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: SUBSS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0x5c, 0xc0}},
1141 {name: "TESTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x85, 0xc0}},
1142 {name: "TESTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x85, 0xc0}},
1143 {name: "TESTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x85, 0xc0}},
1144 {name: "TESTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TESTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x85, 0xc0}},
1145 {name: "TESTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x85, 0xc0}},
1146 {name: "TESTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x85, 0xc0}},
1147 {name: "TESTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x85, 0xc0}},
1148 {name: "TESTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TESTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x85, 0xc0}},
1149 {name: "TZCNTL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0xf, 0xbc, 0xc0}},
1150 {name: "TZCNTL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x44, 0xf, 0xbc, 0xc0}},
1151 {name: "TZCNTL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x41, 0xf, 0xbc, 0xc0}},
1152 {name: "TZCNTL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x45, 0xf, 0xbc, 0xc0}},
1153 {name: "TZCNTQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x48, 0xf, 0xbc, 0xc0}},
1154 {name: "TZCNTQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4c, 0xf, 0xbc, 0xc0}},
1155 {name: "TZCNTQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0xf3, 0x49, 0xf, 0xbc, 0xc0}},
1156 {name: "TZCNTQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: TZCNTQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0xf3, 0x4d, 0xf, 0xbc, 0xc0}},
1157 {name: "UCOMISD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x2e, 0xc0}},
1158 {name: "UCOMISD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x2e, 0xc0}},
1159 {name: "UCOMISD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0xc0}},
1160 {name: "UCOMISD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x2e, 0xc0}},
1161 {name: "UCOMISS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x2e, 0xc0}},
1162 {name: "UCOMISS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x2e, 0xc0}},
1163 {name: "UCOMISS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x2e, 0xc0}},
1164 {name: "UCOMISS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: UCOMISS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x2e, 0xc0}},
1165 {name: "XORL/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x31, 0xc0}},
1166 {name: "XORL/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x41, 0x31, 0xc0}},
1167 {name: "XORL/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x44, 0x31, 0xc0}},
1168 {name: "XORL/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: XORL, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x45, 0x31, 0xc0}},
1169 {name: "XORPD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x57, 0xc0}},
1170 {name: "XORPD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x57, 0xc0}},
1171 {name: "XORPD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x57, 0xc0}},
1172 {name: "XORPD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: XORPD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x57, 0xc0}},
1173 {name: "XORPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x57, 0xc0}},
1174 {name: "XORPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x57, 0xc0}},
1175 {name: "XORPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x57, 0xc0}},
1176 {name: "XORPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: XORPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x57, 0xc0}},
1177 {name: "XORQ/src=AX/dst=AX/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegAX, dstReg: RegAX, arg: 0x0}, exp: []byte{0x48, 0x31, 0xc0}},
1178 {name: "XORQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x31, 0xc0}},
1179 {name: "XORQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x31, 0xc0}},
1180 {name: "XORQ/src=R8/dst=R8/arg=0", n: &nodeImpl{instruction: XORQ, srcReg: RegR8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x31, 0xc0}},
1181 {name: "XCHGQ/src=R8/dst=AX/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x4c, 0x87, 0xc0}},
1182 {name: "XCHGQ/src=AX/dst=R8/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegAX, dstReg: RegR8, arg: 0x0}, exp: []byte{0x49, 0x87, 0xc0}},
1183 {name: "XCHGQ/src=R8/dst=R9/arg=0", n: &nodeImpl{instruction: XCHGQ, srcReg: RegR9, dstReg: RegR8, arg: 0x0}, exp: []byte{0x4d, 0x87, 0xc8}},
1184 {name: "PXOR/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xef, 0xc0}},
1185 {name: "PXOR/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xef, 0xc0}},
1186 {name: "PXOR/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PXOR, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xef, 0xc0}},
1187 {name: "PSHUFB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x0, 0xc0}},
1188 {name: "PSHUFB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x0, 0xc0}},
1189 {name: "PSHUFB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x0, 0xc0}},
1190 {name: "PSHUFB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x0, 0xc0}},
1191 {name: "PSHUFD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x70, 0xc0, 0x0}},
1192 {name: "PSHUFD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x70, 0xc0, 0x0}},
1193 {name: "PSHUFD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x70, 0xc0, 0x0}},
1194 {name: "PSHUFD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x70, 0xc0, 0x0}},
1195 {name: "PSHUFD/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x70, 0xc0, 0x1}},
1196 {name: "PSHUFD/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x70, 0xc0, 0x1}},
1197 {name: "PSHUFD/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x70, 0xc0, 0x1}},
1198 {name: "PSHUFD/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: PSHUFD, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x70, 0xc0, 0x1}},
1199 {name: "PEXTRB/src=X0/dst=AX/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x14, 0xc0, 0x0}},
1200 {name: "PEXTRB/src=X0/dst=R8/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX0, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x14, 0xc0, 0x0}},
1201 {name: "PEXTRB/src=X8/dst=AX/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX8, dstReg: RegAX, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x14, 0xc0, 0x0}},
1202 {name: "PEXTRB/src=X8/dst=R8/arg=0", n: &nodeImpl{instruction: PEXTRB, srcReg: RegX8, dstReg: RegR8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x14, 0xc0, 0x0}},
1203 {name: "PEXTRW/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0xf, 0xc5, 0xc0, 0x1}},
1204 {name: "PEXTRW/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0xc5, 0xc0, 0x1}},
1205 {name: "PEXTRW/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0xc5, 0xc0, 0x1}},
1206 {name: "PEXTRW/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRW, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0xc5, 0xc0, 0x1}},
1207 {name: "PEXTRD/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
1208 {name: "PEXTRD/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
1209 {name: "PEXTRD/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
1210 {name: "PEXTRD/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRD, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
1211 {name: "PEXTRQ/src=X0/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
1212 {name: "PEXTRQ/src=X0/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX0, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x49, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
1213 {name: "PEXTRQ/src=X8/dst=AX/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX8, dstReg: RegAX, arg: 0x1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
1214 {name: "PEXTRQ/src=X8/dst=R8/arg=1", n: &nodeImpl{instruction: PEXTRQ, srcReg: RegX8, dstReg: RegR8, arg: 0x1}, exp: []byte{0x66, 0x4d, 0xf, 0x3a, 0x16, 0xc0, 0x1}},
1215 {name: "MOVLHPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf, 0x16, 0xc0}},
1216 {name: "MOVLHPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x44, 0xf, 0x16, 0xc0}},
1217 {name: "MOVLHPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x41, 0xf, 0x16, 0xc0}},
1218 {name: "MOVLHPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVLHPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x45, 0xf, 0x16, 0xc0}},
1219 {name: "INSERTPS/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x3a, 0x21, 0xc0, 0x0}},
1220 {name: "INSERTPS/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x21, 0xc0, 0x0}},
1221 {name: "INSERTPS/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x21, 0xc0, 0x0}},
1222 {name: "INSERTPS/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x21, 0xc0, 0x0}},
1223 {name: "INSERTPS/src=X0/dst=X0/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0xf, 0x3a, 0x21, 0xc0, 0x1}},
1224 {name: "INSERTPS/src=X0/dst=X8/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX0, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x21, 0xc0, 0x1}},
1225 {name: "INSERTPS/src=X8/dst=X0/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX0, arg: 0x1}, exp: []byte{0x66, 0x41, 0xf, 0x3a, 0x21, 0xc0, 0x1}},
1226 {name: "INSERTPS/src=X8/dst=X8/arg=1", n: &nodeImpl{instruction: INSERTPS, srcReg: RegX8, dstReg: RegX8, arg: 0x1}, exp: []byte{0x66, 0x45, 0xf, 0x3a, 0x21, 0xc0, 0x1}},
1227 {name: "PTEST/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x17, 0xc0}},
1228 {name: "PTEST/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x17, 0xc0}},
1229 {name: "PTEST/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x17, 0xc0}},
1230 {name: "PTEST/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PTEST, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x17, 0xc0}},
1231 {name: "PCMPEQB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x74, 0xc0}},
1232 {name: "PCMPEQB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x74, 0xc0}},
1233 {name: "PCMPEQB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x74, 0xc0}},
1234 {name: "PCMPEQB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x74, 0xc0}},
1235 {name: "PCMPEQW/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x75, 0xc0}},
1236 {name: "PCMPEQW/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x75, 0xc0}},
1237 {name: "PCMPEQW/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x75, 0xc0}},
1238 {name: "PCMPEQW/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQW, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x75, 0xc0}},
1239 {name: "PCMPEQD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x76, 0xc0}},
1240 {name: "PCMPEQD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x76, 0xc0}},
1241 {name: "PCMPEQD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x76, 0xc0}},
1242 {name: "PCMPEQD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x76, 0xc0}},
1243 {name: "PCMPEQQ/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0x38, 0x29, 0xc0}},
1244 {name: "PCMPEQQ/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0x38, 0x29, 0xc0}},
1245 {name: "PCMPEQQ/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x29, 0xc0}},
1246 {name: "PCMPEQQ/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PCMPEQQ, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0x38, 0x29, 0xc0}},
1247 {name: "PADDUSB/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0xf, 0xdc, 0xc0}},
1248 {name: "PADDUSB/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x44, 0xf, 0xdc, 0xc0}},
1249 {name: "PADDUSB/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0x66, 0x41, 0xf, 0xdc, 0xc0}},
1250 {name: "PADDUSB/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: PADDUSB, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0x66, 0x45, 0xf, 0xdc, 0xc0}},
1251 {name: "MOVSD/src=X0/dst=X0/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX0, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0xf, 0x10, 0xc0}},
1252 {name: "MOVSD/src=X0/dst=X8/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX0, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x44, 0xf, 0x10, 0xc0}},
1253 {name: "MOVSD/src=X8/dst=X0/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX8, dstReg: RegX0, arg: 0x0}, exp: []byte{0xf2, 0x41, 0xf, 0x10, 0xc0}},
1254 {name: "MOVSD/src=X8/dst=X8/arg=0", n: &nodeImpl{instruction: MOVSD, srcReg: RegX8, dstReg: RegX8, arg: 0x0}, exp: []byte{0xf2, 0x45, 0xf, 0x10, 0xc0}},
1255 }
1256
1257 code := asm.CodeSegment{}
1258 defer func() { require.NoError(t, code.Unmap()) }()
1259
1260 for _, tt := range tests {
1261 tc := tt
1262 a := NewAssembler()
1263 buf := code.NextCodeSection()
1264 err := a.encodeRegisterToRegister(buf, tc.n)
1265 require.NoError(t, err, tc.name)
1266
1267 err = a.Assemble(buf)
1268 require.NoError(t, err, tc.name)
1269
1270 actual := buf.Bytes()
1271 require.Equal(t, tc.exp, actual, tc.name)
1272 }
1273 }
1274
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