Source file src/github.com/tetratelabs/wazero/internal/asm/amd64/impl_1_test.go

Documentation: github.com/tetratelabs/wazero/internal/asm/amd64

     1  package amd64
     2  
     3  import (
     4  	"strconv"
     5  	"testing"
     6  
     7  	"github.com/tetratelabs/wazero/internal/asm"
     8  	"github.com/tetratelabs/wazero/internal/testing/require"
     9  )
    10  
    11  func TestNodePool_allocNode(t *testing.T) {
    12  	np := nodePool{index: nodePageSize}
    13  
    14  	for i := 0; i < nodePageSize; i++ {
    15  		n := np.allocNode()
    16  		require.Equal(t, &np.pages[0][i], n)
    17  		require.Equal(t, i+1, np.index)
    18  		require.Equal(t, 1, len(np.pages))
    19  	}
    20  	require.Equal(t, nodePageSize, np.index)
    21  
    22  	// Reached the next page.
    23  	secondPageBegin := np.allocNode()
    24  	require.Equal(t, 1, np.index)
    25  	require.Equal(t, 2, len(np.pages))
    26  	require.Equal(t, &np.pages[1][0], secondPageBegin)
    27  }
    28  
    29  func TestAssemblerImpl_Reset(t *testing.T) {
    30  	// Existing values.
    31  	code := asm.CodeSegment{}
    32  	defer func() { require.NoError(t, code.Unmap()) }()
    33  
    34  	buf := code.NextCodeSection()
    35  	buf.AppendBytes([]byte{0, 0, 0, 0, 0})
    36  
    37  	staticConsts := asm.NewStaticConstPool()
    38  	staticConsts.AddConst(asm.NewStaticConst(nil), 1234)
    39  	readInstructionAddressNodes := make([]*nodeImpl, 5)
    40  	ba := asm.BaseAssemblerImpl{
    41  		SetBranchTargetOnNextNodes: make([]asm.Node, 5),
    42  		JumpTableEntries:           make([]asm.JumpTableEntry, 10),
    43  	}
    44  
    45  	// Create assembler and reset.
    46  	a := &AssemblerImpl{
    47  		nodePool: nodePool{
    48  			pages: []*nodePage{new(nodePage), new(nodePage)},
    49  			index: 12,
    50  		},
    51  		pool:                        staticConsts,
    52  		readInstructionAddressNodes: readInstructionAddressNodes,
    53  		BaseAssemblerImpl:           ba,
    54  	}
    55  	a.Reset()
    56  	buf.Reset()
    57  
    58  	// Check each field.
    59  	require.Equal(t, 65536, buf.Cap())
    60  	require.Equal(t, 0, buf.Len())
    61  
    62  	require.Zero(t, len(a.nodePool.pages))
    63  	require.Equal(t, nodePageSize, a.nodePool.index)
    64  
    65  	require.NotEqual(t, staticConsts, a.pool)
    66  
    67  	require.Equal(t, 0, len(a.readInstructionAddressNodes))
    68  	require.Equal(t, cap(readInstructionAddressNodes), cap(a.readInstructionAddressNodes))
    69  
    70  	require.Equal(t, 0, len(a.SetBranchTargetOnNextNodes))
    71  	require.Equal(t, cap(ba.SetBranchTargetOnNextNodes), cap(a.SetBranchTargetOnNextNodes))
    72  
    73  	require.Equal(t, 0, len(a.JumpTableEntries))
    74  	require.Equal(t, cap(ba.JumpTableEntries), cap(a.JumpTableEntries))
    75  }
    76  
    77  func TestNodeImpl_AssignJumpTarget(t *testing.T) {
    78  	n := &nodeImpl{}
    79  	target := &nodeImpl{}
    80  	n.AssignJumpTarget(target)
    81  	require.Equal(t, n.jumpTarget, target)
    82  }
    83  
    84  func TestNodeImpl_AssignDestinationConstant(t *testing.T) {
    85  	n := &nodeImpl{}
    86  	n.AssignDestinationConstant(12345)
    87  	require.Equal(t, int64(12345), n.dstConst)
    88  }
    89  
    90  func TestNodeImpl_AssignSourceConstant(t *testing.T) {
    91  	n := &nodeImpl{}
    92  	n.AssignSourceConstant(12345)
    93  	require.Equal(t, int64(12345), n.srcConst)
    94  }
    95  
    96  func TestAssemblerImpl_Assemble(t *testing.T) {
    97  	t.Run("no reassemble", func(t *testing.T) {
    98  		a := NewAssembler()
    99  
   100  		jmp := a.CompileJump(JCC)
   101  		const dummyInstruction = CDQ
   102  		a.CompileStandAlone(dummyInstruction)
   103  		a.CompileStandAlone(dummyInstruction)
   104  		a.CompileStandAlone(dummyInstruction)
   105  		target := a.CompileStandAlone(dummyInstruction)
   106  		jmp.AssignJumpTarget(target)
   107  
   108  		code := asm.CodeSegment{}
   109  		defer func() { require.NoError(t, code.Unmap()) }()
   110  
   111  		buf := code.NextCodeSection()
   112  		err := a.Assemble(buf)
   113  		require.NoError(t, err)
   114  
   115  		actual := buf.Bytes()
   116  		require.Equal(t, []byte{0x73, 0x3, 0x99, 0x99, 0x99, 0x99}, actual)
   117  	})
   118  	t.Run("re-assemble", func(t *testing.T) {
   119  		a := NewAssembler()
   120  		jmp := a.CompileJump(JCC)
   121  		const dummyInstruction = CDQ
   122  		// Ensure that at least 128 bytes between JCC and the target which results in
   123  		// reassemble as we have to convert the forward jump as long variant.
   124  		for i := 0; i < 128; i++ {
   125  			a.CompileStandAlone(dummyInstruction)
   126  		}
   127  		jmp.AssignJumpTarget(a.CompileStandAlone(dummyInstruction))
   128  
   129  		a.initializeNodesForEncoding()
   130  
   131  		code := asm.CodeSegment{}
   132  		defer func() { require.NoError(t, code.Unmap()) }()
   133  
   134  		// For the first encoding, we must be forced to reassemble.
   135  		err := a.encode(code.NextCodeSection())
   136  		require.NoError(t, err)
   137  		require.True(t, a.forceReAssemble)
   138  	})
   139  }
   140  
   141  func TestNodeImpl_String(t *testing.T) {
   142  	tests := []struct {
   143  		in  *nodeImpl
   144  		exp string
   145  	}{
   146  		{
   147  			in:  &nodeImpl{instruction: NOP},
   148  			exp: "NOP",
   149  		},
   150  		{
   151  			in:  &nodeImpl{instruction: SETCC, types: operandTypesNoneToRegister, dstReg: RegAX},
   152  			exp: "SETCC AX",
   153  		},
   154  		{
   155  			in:  &nodeImpl{instruction: JMP, types: operandTypesNoneToMemory, dstReg: RegAX, dstConst: 100},
   156  			exp: "JMP [AX + 0x64]",
   157  		},
   158  		{
   159  			in:  &nodeImpl{instruction: JMP, types: operandTypesNoneToMemory, dstReg: RegAX, dstConst: 100, dstMemScale: 8, dstMemIndex: RegR11},
   160  			exp: "JMP [AX + 0x64 + R11*0x8]",
   161  		},
   162  		{
   163  			in:  &nodeImpl{instruction: JMP, types: operandTypesNoneToBranch, jumpTarget: &nodeImpl{instruction: JMP, types: operandTypesNoneToMemory, dstReg: RegAX, dstConst: 100}},
   164  			exp: "JMP {JMP [AX + 0x64]}",
   165  		},
   166  		{
   167  			in:  &nodeImpl{instruction: IDIVQ, types: operandTypesRegisterToNone, srcReg: RegDX},
   168  			exp: "IDIVQ DX",
   169  		},
   170  		{
   171  			in:  &nodeImpl{instruction: ADDL, types: operandTypesRegisterToRegister, srcReg: RegDX, dstReg: RegR14},
   172  			exp: "ADDL DX, R14",
   173  		},
   174  		{
   175  			in: &nodeImpl{
   176  				instruction: MOVQ, types: operandTypesRegisterToMemory,
   177  				srcReg: RegDX, dstReg: RegR14, dstConst: 100,
   178  			},
   179  			exp: "MOVQ DX, [R14 + 0x64]",
   180  		},
   181  		{
   182  			in: &nodeImpl{
   183  				instruction: MOVQ, types: operandTypesRegisterToMemory,
   184  				srcReg: RegDX, dstReg: RegR14, dstConst: 100, dstMemIndex: RegCX, dstMemScale: 4,
   185  			},
   186  			exp: "MOVQ DX, [R14 + 0x64 + CX*0x4]",
   187  		},
   188  		{
   189  			in: &nodeImpl{
   190  				instruction: CMPL, types: operandTypesRegisterToConst,
   191  				srcReg: RegDX, dstConst: 100,
   192  			},
   193  			exp: "CMPL DX, 0x64",
   194  		},
   195  		{
   196  			in: &nodeImpl{
   197  				instruction: MOVL, types: operandTypesMemoryToRegister,
   198  				srcReg: RegDX, srcConst: 1, dstReg: RegAX,
   199  			},
   200  			exp: "MOVL [DX + 0x1], AX",
   201  		},
   202  		{
   203  			in: &nodeImpl{
   204  				instruction: MOVL, types: operandTypesMemoryToRegister,
   205  				srcReg: RegDX, srcConst: 1, srcMemIndex: RegR12, srcMemScale: 2,
   206  				dstReg: RegAX,
   207  			},
   208  			exp: "MOVL [DX + 0x1 + R12*0x2], AX",
   209  		},
   210  		{
   211  			in: &nodeImpl{
   212  				instruction: CMPQ, types: operandTypesMemoryToConst,
   213  				srcReg: RegDX, srcConst: 1, srcMemIndex: RegR12, srcMemScale: 2,
   214  				dstConst: 123,
   215  			},
   216  			exp: "CMPQ [DX + 0x1 + R12*0x2], 0x7b",
   217  		},
   218  		{
   219  			in:  &nodeImpl{instruction: CMPQ, types: operandTypesMemoryToConst, srcReg: RegDX, srcConst: 1, dstConst: 123},
   220  			exp: "CMPQ [DX + 0x1], 0x7b",
   221  		},
   222  		{
   223  			in:  &nodeImpl{instruction: MOVQ, types: operandTypesConstToMemory, srcConst: 123, dstReg: RegAX, dstConst: 100, dstMemScale: 8, dstMemIndex: RegR11},
   224  			exp: "MOVQ 0x7b, [AX + 0x64 + R11*0x8]",
   225  		},
   226  		{
   227  			in:  &nodeImpl{instruction: MOVQ, types: operandTypesConstToMemory, srcConst: 123, dstReg: RegAX, dstConst: 100},
   228  			exp: "MOVQ 0x7b, [AX + 0x64]",
   229  		},
   230  		{
   231  			in:  &nodeImpl{instruction: MOVQ, types: operandTypesConstToRegister, srcConst: 123, dstReg: RegAX},
   232  			exp: "MOVQ 0x7b, AX",
   233  		},
   234  		{
   235  			in:  &nodeImpl{instruction: LEAQ, types: operandTypesStaticConstToRegister, staticConst: &asm.StaticConst{Raw: []byte{0xff, 0x01, 0x2, 0xff}}, dstReg: RegAX},
   236  			exp: "LEAQ $0xff0102ff, AX",
   237  		},
   238  		{
   239  			in:  &nodeImpl{instruction: CMPQ, types: operandTypesRegisterToStaticConst, staticConst: &asm.StaticConst{Raw: []byte{0xff, 0x01, 0x2, 0xff}}, srcReg: RegAX},
   240  			exp: "CMPQ AX, $0xff0102ff",
   241  		},
   242  	}
   243  
   244  	for _, tt := range tests {
   245  		tc := tt
   246  		require.Equal(t, tc.exp, tc.in.String())
   247  	}
   248  }
   249  
   250  func TestAssemblerImpl_addNode(t *testing.T) {
   251  	a := NewAssembler()
   252  
   253  	root := &nodeImpl{}
   254  	a.addNode(root)
   255  	require.Equal(t, a.root, root)
   256  	require.Equal(t, a.current, root)
   257  	require.Nil(t, root.next)
   258  
   259  	next := &nodeImpl{}
   260  	a.addNode(next)
   261  	require.Equal(t, a.root, root)
   262  	require.Equal(t, a.current, next)
   263  	require.Equal(t, next, root.next)
   264  	require.Equal(t, next.prev, root)
   265  	require.Nil(t, next.next)
   266  }
   267  
   268  func TestAssemblerImpl_newNode(t *testing.T) {
   269  	a := NewAssembler()
   270  	actual := a.newNode(ADDL, operandTypesConstToMemory)
   271  	require.Equal(t, ADDL, actual.instruction)
   272  	require.Equal(t, operandTypesConstToMemory, actual.types)
   273  	require.Equal(t, actual, a.root)
   274  	require.Equal(t, actual, a.current)
   275  }
   276  
   277  func TestAssemblerImpl_encodeNode(t *testing.T) {
   278  	a := NewAssembler()
   279  	code := asm.CodeSegment{}
   280  	defer func() { require.NoError(t, code.Unmap()) }()
   281  	buf := code.NextCodeSection()
   282  	err := a.encodeNode(buf, &nodeImpl{
   283  		instruction: ADDPD,
   284  		types:       operandTypesRegisterToMemory,
   285  	})
   286  	require.EqualError(t, err, "ADDPD is unsupported for RegisterToMemory type: ADDPD nil, [nil + 0x0]")
   287  }
   288  
   289  func TestAssemblerImpl_padNOP(t *testing.T) {
   290  	tests := []struct {
   291  		num      int
   292  		expected []byte
   293  	}{
   294  		{num: 1, expected: nopOpcodes[0][:1]},
   295  		{num: 2, expected: nopOpcodes[1][:2]},
   296  		{num: 3, expected: nopOpcodes[2][:3]},
   297  		{num: 4, expected: nopOpcodes[3][:4]},
   298  		{num: 5, expected: nopOpcodes[4][:5]},
   299  		{num: 6, expected: nopOpcodes[5][:6]},
   300  		{num: 7, expected: nopOpcodes[6][:7]},
   301  		{num: 8, expected: nopOpcodes[7][:8]},
   302  		{num: 9, expected: nopOpcodes[8][:9]},
   303  		{num: 10, expected: nopOpcodes[9][:10]},
   304  		{num: 11, expected: nopOpcodes[10][:11]},
   305  		{num: 12, expected: append(nopOpcodes[10][:11], nopOpcodes[0][:1]...)},
   306  		{num: 13, expected: append(nopOpcodes[10][:11], nopOpcodes[1][:2]...)},
   307  		{num: 14, expected: append(nopOpcodes[10][:11], nopOpcodes[2][:3]...)},
   308  		{num: 15, expected: append(nopOpcodes[10][:11], nopOpcodes[3][:4]...)},
   309  		{num: 16, expected: append(nopOpcodes[10][:11], nopOpcodes[4][:5]...)},
   310  		{num: 17, expected: append(nopOpcodes[10][:11], nopOpcodes[5][:6]...)},
   311  		{num: 18, expected: append(nopOpcodes[10][:11], nopOpcodes[6][:7]...)},
   312  		{num: 19, expected: append(nopOpcodes[10][:11], nopOpcodes[7][:8]...)},
   313  		{num: 20, expected: append(nopOpcodes[10][:11], nopOpcodes[8][:9]...)},
   314  	}
   315  
   316  	for _, tt := range tests {
   317  		tc := tt
   318  		t.Run(strconv.Itoa(tc.num), func(t *testing.T) {
   319  			code := asm.CodeSegment{}
   320  			defer func() { require.NoError(t, code.Unmap()) }()
   321  
   322  			buf := code.NextCodeSection()
   323  
   324  			a := NewAssembler()
   325  			a.padNOP(buf, tc.num)
   326  
   327  			actual := buf.Bytes()
   328  			require.Equal(t, tc.expected, actual)
   329  		})
   330  	}
   331  }
   332  
   333  func TestAssemblerImpl_CompileStandAlone(t *testing.T) {
   334  	a := NewAssembler()
   335  	a.CompileStandAlone(RET)
   336  	actualNode := a.current
   337  	require.Equal(t, RET, actualNode.instruction)
   338  	require.Equal(t, operandTypesNoneToNone, actualNode.types)
   339  }
   340  
   341  func TestAssemblerImpl_CompileConstToRegister(t *testing.T) {
   342  	a := NewAssembler()
   343  	a.CompileConstToRegister(MOVQ, 1000, RegAX)
   344  	actualNode := a.current
   345  	require.Equal(t, MOVQ, actualNode.instruction)
   346  	require.Equal(t, int64(1000), actualNode.srcConst)
   347  	require.Equal(t, RegAX, actualNode.dstReg)
   348  	require.Equal(t, operandTypesConstToRegister, actualNode.types)
   349  }
   350  
   351  func TestAssemblerImpl_CompileRegisterToRegister(t *testing.T) {
   352  	a := NewAssembler()
   353  	a.CompileRegisterToRegister(MOVQ, RegBX, RegAX)
   354  	actualNode := a.current
   355  	require.Equal(t, MOVQ, actualNode.instruction)
   356  	require.Equal(t, RegBX, actualNode.srcReg)
   357  	require.Equal(t, RegAX, actualNode.dstReg)
   358  	require.Equal(t, operandTypesRegisterToRegister, actualNode.types)
   359  }
   360  
   361  func TestAssemblerImpl_CompileMemoryToRegister(t *testing.T) {
   362  	a := NewAssembler()
   363  	a.CompileMemoryToRegister(MOVQ, RegBX, 100, RegAX)
   364  	actualNode := a.current
   365  	require.Equal(t, MOVQ, actualNode.instruction)
   366  	require.Equal(t, RegBX, actualNode.srcReg)
   367  	require.Equal(t, int64(100), actualNode.srcConst)
   368  	require.Equal(t, RegAX, actualNode.dstReg)
   369  	require.Equal(t, operandTypesMemoryToRegister, actualNode.types)
   370  }
   371  
   372  func TestAssemblerImpl_CompileRegisterToMemory(t *testing.T) {
   373  	a := NewAssembler()
   374  	a.CompileRegisterToMemory(MOVQ, RegBX, RegAX, 100)
   375  	actualNode := a.current
   376  	require.Equal(t, MOVQ, actualNode.instruction)
   377  	require.Equal(t, RegBX, actualNode.srcReg)
   378  	require.Equal(t, RegAX, actualNode.dstReg)
   379  	require.Equal(t, int64(100), actualNode.dstConst)
   380  	require.Equal(t, operandTypesRegisterToMemory, actualNode.types)
   381  }
   382  
   383  func TestAssemblerImpl_CompileJump(t *testing.T) {
   384  	a := NewAssembler()
   385  	a.CompileJump(JMP)
   386  	actualNode := a.current
   387  	require.Equal(t, JMP, actualNode.instruction)
   388  	require.Equal(t, operandTypesNoneToBranch, actualNode.types)
   389  }
   390  
   391  func TestAssemblerImpl_CompileJumpToRegister(t *testing.T) {
   392  	a := NewAssembler()
   393  	a.CompileJumpToRegister(JNE, RegAX)
   394  	actualNode := a.current
   395  	require.Equal(t, JNE, actualNode.instruction)
   396  	require.Equal(t, RegAX, actualNode.dstReg)
   397  	require.Equal(t, operandTypesNoneToRegister, actualNode.types)
   398  }
   399  
   400  func TestAssemblerImpl_CompileJumpToMemory(t *testing.T) {
   401  	a := NewAssembler()
   402  	a.CompileJumpToMemory(JNE, RegAX, 100)
   403  	actualNode := a.current
   404  	require.Equal(t, JNE, actualNode.instruction)
   405  	require.Equal(t, RegAX, actualNode.dstReg)
   406  	require.Equal(t, int64(100), actualNode.dstConst)
   407  	require.Equal(t, operandTypesNoneToMemory, actualNode.types)
   408  }
   409  
   410  func TestAssemblerImpl_CompileReadInstructionAddress(t *testing.T) {
   411  	a := NewAssembler()
   412  	a.CompileReadInstructionAddress(RegR10, RET)
   413  	actualNode := a.current
   414  	require.Equal(t, LEAQ, actualNode.instruction)
   415  	require.Equal(t, RegR10, actualNode.dstReg)
   416  	require.Equal(t, operandTypesMemoryToRegister, actualNode.types)
   417  	require.Equal(t, RET, actualNode.readInstructionAddressBeforeTargetInstruction)
   418  }
   419  
   420  func TestAssemblerImpl_CompileRegisterToRegisterWithArg(t *testing.T) {
   421  	a := NewAssembler()
   422  	a.CompileRegisterToRegisterWithArg(MOVQ, RegBX, RegAX, 123)
   423  	actualNode := a.current
   424  	require.Equal(t, MOVQ, actualNode.instruction)
   425  	require.Equal(t, RegBX, actualNode.srcReg)
   426  	require.Equal(t, RegAX, actualNode.dstReg)
   427  	require.Equal(t, byte(123), actualNode.arg)
   428  	require.Equal(t, operandTypesRegisterToRegister, actualNode.types)
   429  }
   430  
   431  func TestAssemblerImpl_CompileMemoryWithIndexToRegister(t *testing.T) {
   432  	a := NewAssembler()
   433  	a.CompileMemoryWithIndexToRegister(MOVQ, RegBX, 100, RegR10, 8, RegAX)
   434  	actualNode := a.current
   435  	require.Equal(t, MOVQ, actualNode.instruction)
   436  	require.Equal(t, RegBX, actualNode.srcReg)
   437  	require.Equal(t, int64(100), actualNode.srcConst)
   438  	require.Equal(t, RegR10, actualNode.srcMemIndex)
   439  	require.Equal(t, byte(8), actualNode.srcMemScale)
   440  	require.Equal(t, RegAX, actualNode.dstReg)
   441  	require.Equal(t, operandTypesMemoryToRegister, actualNode.types)
   442  }
   443  
   444  func TestAssemblerImpl_CompileRegisterToConst(t *testing.T) {
   445  	a := NewAssembler()
   446  	a.CompileRegisterToConst(MOVQ, RegBX, 123)
   447  	actualNode := a.current
   448  	require.Equal(t, RegBX, actualNode.srcReg)
   449  	require.Equal(t, int64(123), actualNode.dstConst)
   450  	require.Equal(t, operandTypesRegisterToConst, actualNode.types)
   451  }
   452  
   453  func TestAssemblerImpl_CompileRegisterToNone(t *testing.T) {
   454  	a := NewAssembler()
   455  	a.CompileRegisterToNone(MOVQ, RegBX)
   456  	actualNode := a.current
   457  	require.Equal(t, RegBX, actualNode.srcReg)
   458  	require.Equal(t, operandTypesRegisterToNone, actualNode.types)
   459  }
   460  
   461  func TestAssemblerImpl_CompileNoneToRegister(t *testing.T) {
   462  	a := NewAssembler()
   463  	a.CompileNoneToRegister(MOVQ, RegBX)
   464  	actualNode := a.current
   465  	require.Equal(t, RegBX, actualNode.dstReg)
   466  	require.Equal(t, operandTypesNoneToRegister, actualNode.types)
   467  }
   468  
   469  func TestAssemblerImpl_CompileNoneToMemory(t *testing.T) {
   470  	a := NewAssembler()
   471  	a.CompileNoneToMemory(MOVQ, RegBX, 1234)
   472  	actualNode := a.current
   473  	require.Equal(t, RegBX, actualNode.dstReg)
   474  	require.Equal(t, int64(1234), actualNode.dstConst)
   475  	require.Equal(t, operandTypesNoneToMemory, actualNode.types)
   476  }
   477  
   478  func TestAssemblerImpl_CompileConstToMemory(t *testing.T) {
   479  	a := NewAssembler()
   480  	a.CompileConstToMemory(MOVQ, -9999, RegBX, 1234)
   481  	actualNode := a.current
   482  	require.Equal(t, RegBX, actualNode.dstReg)
   483  	require.Equal(t, int64(-9999), actualNode.srcConst)
   484  	require.Equal(t, int64(1234), actualNode.dstConst)
   485  	require.Equal(t, operandTypesConstToMemory, actualNode.types)
   486  }
   487  
   488  func TestAssemblerImpl_CompileMemoryToConst(t *testing.T) {
   489  	a := NewAssembler()
   490  	a.CompileMemoryToConst(MOVQ, RegBX, 1234, -9999)
   491  	actualNode := a.current
   492  	require.Equal(t, RegBX, actualNode.srcReg)
   493  	require.Equal(t, int64(1234), actualNode.srcConst)
   494  	require.Equal(t, int64(-9999), actualNode.dstConst)
   495  	require.Equal(t, operandTypesMemoryToConst, actualNode.types)
   496  }
   497  
   498  func TestAssemblerImpl_encodeNoneToNone(t *testing.T) {
   499  	tests := []struct {
   500  		inst   asm.Instruction
   501  		exp    []byte
   502  		expErr bool
   503  	}{
   504  		{inst: ADDL, expErr: true},
   505  		{inst: CDQ, exp: []byte{0x99}},
   506  		{inst: CQO, exp: []byte{0x48, 0x99}},
   507  		{inst: NOP, exp: nil},
   508  		{inst: RET, exp: []byte{0xc3}},
   509  		{inst: REPMOVSQ, exp: []byte{0xf3, rexPrefixW, 0xa5}},
   510  		{inst: REPSTOSQ, exp: []byte{0xf3, rexPrefixW, 0xab}},
   511  		{inst: STD, exp: []byte{0xfd}},
   512  		{inst: CLD, exp: []byte{0xfc}},
   513  	}
   514  
   515  	for _, tt := range tests {
   516  		tc := tt
   517  		t.Run(InstructionName(tc.inst), func(t *testing.T) {
   518  			code := asm.CodeSegment{}
   519  			defer func() { require.NoError(t, code.Unmap()) }()
   520  
   521  			a := NewAssembler()
   522  			buf := code.NextCodeSection()
   523  			err := a.encodeNoneToNone(buf, &nodeImpl{instruction: tc.inst, types: operandTypesNoneToNone})
   524  			if tc.expErr {
   525  				require.Error(t, err)
   526  			} else {
   527  				require.NoError(t, err)
   528  				require.Equal(t, tc.exp, buf.Bytes())
   529  			}
   530  		})
   531  	}
   532  }
   533  
   534  func TestAssemblerImpl_EncodeMemoryToRegister(t *testing.T) {
   535  	tests := []struct {
   536  		name string
   537  		n    *nodeImpl
   538  		exp  []byte
   539  	}{
   540  		{name: "MOVDQU", n: &nodeImpl{instruction: MOVDQU, srcReg: RegAX, dstReg: RegX3, srcConst: 10}, exp: []byte{0xf3, 0xf, 0x6f, 0x58, 0xa}},
   541  		{name: "MOVDQU/2", n: &nodeImpl{instruction: MOVDQU, srcReg: RegR13, dstReg: RegX3, srcConst: 10}, exp: []byte{0xf3, 0x41, 0xf, 0x6f, 0x5d, 0xa}},
   542  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x20, 0x0}},
   543  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x20, 0x1}},
   544  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x20, 0x1, 0x0}},
   545  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x20, 0x1, 0x1}},
   546  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   547  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   548  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x0, 0x0}},
   549  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x0, 0x1}},
   550  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x0, 0x1, 0x0}},
   551  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x0, 0x1, 0x1}},
   552  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   553  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   554  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x28, 0x0}},
   555  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x28, 0x1}},
   556  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x28, 0x1, 0x0}},
   557  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x28, 0x1, 0x1}},
   558  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   559  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   560  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x30, 0x0}},
   561  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x30, 0x1}},
   562  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x30, 0x1, 0x0}},
   563  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x30, 0x1, 0x1}},
   564  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   565  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   566  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x20, 0x0}},
   567  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x20, 0x1}},
   568  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x20, 0x1, 0x0}},
   569  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x20, 0x1, 0x1}},
   570  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   571  		{name: "PINSRB/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   572  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x0, 0x0}},
   573  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x0, 0x1}},
   574  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x0, 0x1, 0x0}},
   575  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x0, 0x1, 0x1}},
   576  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   577  		{name: "PINSRB/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   578  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x28, 0x0}},
   579  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x28, 0x1}},
   580  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x28, 0x1, 0x0}},
   581  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x28, 0x1, 0x1}},
   582  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   583  		{name: "PINSRB/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   584  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x30, 0x0}},
   585  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x30, 0x1}},
   586  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x30, 0x1, 0x0}},
   587  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x30, 0x1, 0x1}},
   588  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   589  		{name: "PINSRB/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   590  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x60, 0x0}},
   591  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0x60, 0x1}},
   592  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x60, 0x1, 0x0}},
   593  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0x60, 0x1, 0x1}},
   594  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   595  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   596  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x40, 0x0}},
   597  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x40, 0x1}},
   598  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x40, 0x1, 0x0}},
   599  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x40, 0x1, 0x1}},
   600  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   601  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   602  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x68, 0x0}},
   603  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x68, 0x1}},
   604  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x68, 0x1, 0x0}},
   605  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x68, 0x1, 0x1}},
   606  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   607  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   608  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x70, 0x0}},
   609  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x70, 0x1}},
   610  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x70, 0x1, 0x0}},
   611  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x70, 0x1, 0x1}},
   612  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   613  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   614  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x60, 0x0}},
   615  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0x60, 0x1}},
   616  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x60, 0x1, 0x0}},
   617  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0x60, 0x1, 0x1}},
   618  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   619  		{name: "PINSRB/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   620  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x40, 0x0}},
   621  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x40, 0x1}},
   622  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x40, 0x1, 0x0}},
   623  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x40, 0x1, 0x1}},
   624  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   625  		{name: "PINSRB/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   626  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x68, 0x0}},
   627  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x68, 0x1}},
   628  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x68, 0x1, 0x0}},
   629  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x68, 0x1, 0x1}},
   630  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   631  		{name: "PINSRB/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   632  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x70, 0x0}},
   633  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x70, 0x1}},
   634  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x70, 0x1, 0x0}},
   635  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x70, 0x1, 0x1}},
   636  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   637  		{name: "PINSRB/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   638  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xa0, 0x0}},
   639  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xa0, 0x1}},
   640  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xa0, 0x1, 0x0}},
   641  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xa0, 0x1, 0x1}},
   642  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   643  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   644  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x80, 0x0}},
   645  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0x80, 0x1}},
   646  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x80, 0x1, 0x0}},
   647  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0x80, 0x1, 0x1}},
   648  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   649  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   650  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xa8, 0x0}},
   651  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xa8, 0x1}},
   652  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xa8, 0x1, 0x0}},
   653  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xa8, 0x1, 0x1}},
   654  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   655  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   656  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xb0, 0x0}},
   657  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xb0, 0x1}},
   658  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xb0, 0x1, 0x0}},
   659  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xb0, 0x1, 0x1}},
   660  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   661  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   662  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xa0, 0x0}},
   663  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xa0, 0x1}},
   664  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xa0, 0x1, 0x0}},
   665  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xa0, 0x1, 0x1}},
   666  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   667  		{name: "PINSRB/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   668  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x80, 0x0}},
   669  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0x80, 0x1}},
   670  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x80, 0x1, 0x0}},
   671  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0x80, 0x1, 0x1}},
   672  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   673  		{name: "PINSRB/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   674  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xa8, 0x0}},
   675  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xa8, 0x1}},
   676  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xa8, 0x1, 0x0}},
   677  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xa8, 0x1, 0x1}},
   678  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   679  		{name: "PINSRB/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   680  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xb0, 0x0}},
   681  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xb0, 0x1}},
   682  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xb0, 0x1, 0x0}},
   683  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xb0, 0x1, 0x1}},
   684  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   685  		{name: "PINSRB/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   686  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xe0, 0x0}},
   687  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x4, 0xe0, 0x1}},
   688  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xe0, 0x1, 0x0}},
   689  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x44, 0xe0, 0x1, 0x1}},
   690  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   691  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x20, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   692  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xc0, 0x0}},
   693  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xc0, 0x1}},
   694  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xc0, 0x1, 0x0}},
   695  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xc0, 0x1, 0x1}},
   696  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   697  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   698  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xe8, 0x0}},
   699  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xe8, 0x1}},
   700  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xe8, 0x1, 0x0}},
   701  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xe8, 0x1, 0x1}},
   702  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   703  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   704  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xf0, 0x0}},
   705  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x4, 0xf0, 0x1}},
   706  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xf0, 0x1, 0x0}},
   707  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x44, 0xf0, 0x1, 0x1}},
   708  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   709  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x20, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   710  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xe0, 0x0}},
   711  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x2c, 0xe0, 0x1}},
   712  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xe0, 0x1, 0x0}},
   713  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0x6c, 0xe0, 0x1, 0x1}},
   714  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   715  		{name: "PINSRB/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x20, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   716  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xc0, 0x0}},
   717  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xc0, 0x1}},
   718  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xc0, 0x1, 0x0}},
   719  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xc0, 0x1, 0x1}},
   720  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   721  		{name: "PINSRB/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   722  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xe8, 0x0}},
   723  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xe8, 0x1}},
   724  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xe8, 0x1, 0x0}},
   725  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xe8, 0x1, 0x1}},
   726  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   727  		{name: "PINSRB/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   728  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xf0, 0x0}},
   729  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x2c, 0xf0, 0x1}},
   730  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xf0, 0x1, 0x0}},
   731  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0x6c, 0xf0, 0x1, 0x1}},
   732  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   733  		{name: "PINSRB/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRB, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x20, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   734  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x20, 0x0}},
   735  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x20, 0x1}},
   736  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x20, 0x1, 0x0}},
   737  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x20, 0x1, 0x1}},
   738  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   739  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   740  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x0, 0x0}},
   741  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x0, 0x1}},
   742  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x0, 0x1, 0x0}},
   743  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x0, 0x1, 0x1}},
   744  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   745  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   746  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x28, 0x0}},
   747  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x28, 0x1}},
   748  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x28, 0x1, 0x0}},
   749  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x28, 0x1, 0x1}},
   750  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   751  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   752  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x30, 0x0}},
   753  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x30, 0x1}},
   754  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x30, 0x1, 0x0}},
   755  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x30, 0x1, 0x1}},
   756  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   757  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   758  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x20, 0x0}},
   759  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x20, 0x1}},
   760  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x20, 0x1, 0x0}},
   761  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x20, 0x1, 0x1}},
   762  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   763  		{name: "PINSRW/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   764  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x0, 0x0}},
   765  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x0, 0x1}},
   766  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x0, 0x1, 0x0}},
   767  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x0, 0x1, 0x1}},
   768  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   769  		{name: "PINSRW/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   770  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x28, 0x0}},
   771  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x28, 0x1}},
   772  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x28, 0x1, 0x0}},
   773  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x28, 0x1, 0x1}},
   774  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   775  		{name: "PINSRW/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   776  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x30, 0x0}},
   777  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x30, 0x1}},
   778  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x30, 0x1, 0x0}},
   779  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x30, 0x1, 0x1}},
   780  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   781  		{name: "PINSRW/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   782  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x60, 0x0}},
   783  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0x60, 0x1}},
   784  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x60, 0x1, 0x0}},
   785  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0x60, 0x1, 0x1}},
   786  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   787  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   788  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x40, 0x0}},
   789  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x40, 0x1}},
   790  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x40, 0x1, 0x0}},
   791  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x40, 0x1, 0x1}},
   792  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   793  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   794  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x68, 0x0}},
   795  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x68, 0x1}},
   796  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x68, 0x1, 0x0}},
   797  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x68, 0x1, 0x1}},
   798  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   799  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   800  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x70, 0x0}},
   801  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x70, 0x1}},
   802  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x70, 0x1, 0x0}},
   803  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x70, 0x1, 0x1}},
   804  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   805  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   806  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x60, 0x0}},
   807  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0x60, 0x1}},
   808  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x60, 0x1, 0x0}},
   809  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0x60, 0x1, 0x1}},
   810  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   811  		{name: "PINSRW/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   812  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x40, 0x0}},
   813  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x40, 0x1}},
   814  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x40, 0x1, 0x0}},
   815  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x40, 0x1, 0x1}},
   816  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   817  		{name: "PINSRW/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   818  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x68, 0x0}},
   819  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x68, 0x1}},
   820  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x68, 0x1, 0x0}},
   821  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x68, 0x1, 0x1}},
   822  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   823  		{name: "PINSRW/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   824  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x70, 0x0}},
   825  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x70, 0x1}},
   826  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x70, 0x1, 0x0}},
   827  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x70, 0x1, 0x1}},
   828  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   829  		{name: "PINSRW/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   830  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xa0, 0x0}},
   831  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xa0, 0x1}},
   832  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xa0, 0x1, 0x0}},
   833  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xa0, 0x1, 0x1}},
   834  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   835  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   836  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x80, 0x0}},
   837  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0x80, 0x1}},
   838  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x80, 0x1, 0x0}},
   839  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0x80, 0x1, 0x1}},
   840  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   841  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   842  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xa8, 0x0}},
   843  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xa8, 0x1}},
   844  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xa8, 0x1, 0x0}},
   845  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xa8, 0x1, 0x1}},
   846  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   847  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   848  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xb0, 0x0}},
   849  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xb0, 0x1}},
   850  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xb0, 0x1, 0x0}},
   851  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xb0, 0x1, 0x1}},
   852  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   853  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   854  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xa0, 0x0}},
   855  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xa0, 0x1}},
   856  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xa0, 0x1, 0x0}},
   857  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xa0, 0x1, 0x1}},
   858  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   859  		{name: "PINSRW/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   860  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x80, 0x0}},
   861  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0x80, 0x1}},
   862  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x80, 0x1, 0x0}},
   863  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0x80, 0x1, 0x1}},
   864  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   865  		{name: "PINSRW/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   866  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xa8, 0x0}},
   867  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xa8, 0x1}},
   868  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xa8, 0x1, 0x0}},
   869  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xa8, 0x1, 0x1}},
   870  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   871  		{name: "PINSRW/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   872  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xb0, 0x0}},
   873  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xb0, 0x1}},
   874  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xb0, 0x1, 0x0}},
   875  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xb0, 0x1, 0x1}},
   876  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   877  		{name: "PINSRW/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   878  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xe0, 0x0}},
   879  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x4, 0xe0, 0x1}},
   880  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xe0, 0x1, 0x0}},
   881  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x44, 0xe0, 0x1, 0x1}},
   882  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   883  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0xc4, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   884  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xc0, 0x0}},
   885  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xc0, 0x1}},
   886  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xc0, 0x1, 0x0}},
   887  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xc0, 0x1, 0x1}},
   888  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   889  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   890  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xe8, 0x0}},
   891  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xe8, 0x1}},
   892  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xe8, 0x1, 0x0}},
   893  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xe8, 0x1, 0x1}},
   894  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   895  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   896  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xf0, 0x0}},
   897  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x4, 0xf0, 0x1}},
   898  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xf0, 0x1, 0x0}},
   899  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x44, 0xf0, 0x1, 0x1}},
   900  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   901  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0xc4, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   902  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xe0, 0x0}},
   903  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x2c, 0xe0, 0x1}},
   904  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xe0, 0x1, 0x0}},
   905  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0x6c, 0xe0, 0x1, 0x1}},
   906  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   907  		{name: "PINSRW/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0xc4, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   908  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xc0, 0x0}},
   909  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xc0, 0x1}},
   910  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xc0, 0x1, 0x0}},
   911  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xc0, 0x1, 0x1}},
   912  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   913  		{name: "PINSRW/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   914  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xe8, 0x0}},
   915  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xe8, 0x1}},
   916  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xe8, 0x1, 0x0}},
   917  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xe8, 0x1, 0x1}},
   918  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   919  		{name: "PINSRW/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   920  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xf0, 0x0}},
   921  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x2c, 0xf0, 0x1}},
   922  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xf0, 0x1, 0x0}},
   923  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0x6c, 0xf0, 0x1, 0x1}},
   924  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   925  		{name: "PINSRW/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRW, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0xc4, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   926  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x0}},
   927  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x1}},
   928  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x0}},
   929  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x1}},
   930  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   931  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   932  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x0}},
   933  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x1}},
   934  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x0}},
   935  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x1}},
   936  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   937  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   938  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x0}},
   939  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x1}},
   940  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x0}},
   941  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x1}},
   942  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   943  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   944  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x0}},
   945  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x1}},
   946  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x0}},
   947  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x1}},
   948  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   949  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   950  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x0}},
   951  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x1}},
   952  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x0}},
   953  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x1}},
   954  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   955  		{name: "PINSRD/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   956  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x0}},
   957  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x1}},
   958  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x0}},
   959  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x1}},
   960  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   961  		{name: "PINSRD/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   962  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x0}},
   963  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x1}},
   964  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x0}},
   965  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x1}},
   966  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   967  		{name: "PINSRD/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   968  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x0}},
   969  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x1}},
   970  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x0}},
   971  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x1}},
   972  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   973  		{name: "PINSRD/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   974  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x0}},
   975  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x1}},
   976  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x0}},
   977  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x1}},
   978  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   979  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   980  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x0}},
   981  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x1}},
   982  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x0}},
   983  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x1}},
   984  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   985  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   986  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x0}},
   987  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x1}},
   988  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x0}},
   989  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x1}},
   990  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   991  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   992  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x0}},
   993  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x1}},
   994  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x0}},
   995  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x1}},
   996  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}},
   997  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}},
   998  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x0}},
   999  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x1}},
  1000  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x0}},
  1001  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x1}},
  1002  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1003  		{name: "PINSRD/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1004  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x0}},
  1005  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x1}},
  1006  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x0}},
  1007  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x1}},
  1008  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1009  		{name: "PINSRD/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1010  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x0}},
  1011  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x1}},
  1012  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x0}},
  1013  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x1}},
  1014  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1015  		{name: "PINSRD/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1016  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x0}},
  1017  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x1}},
  1018  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x0}},
  1019  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x1}},
  1020  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1021  		{name: "PINSRD/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1022  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x0}},
  1023  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x1}},
  1024  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x0}},
  1025  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x1}},
  1026  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1027  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1028  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x0}},
  1029  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x1}},
  1030  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x0}},
  1031  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x1}},
  1032  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1033  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1034  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x0}},
  1035  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x1}},
  1036  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x0}},
  1037  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x1}},
  1038  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1039  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1040  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x0}},
  1041  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x1}},
  1042  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x0}},
  1043  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x1}},
  1044  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1045  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1046  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x0}},
  1047  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x1}},
  1048  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x0}},
  1049  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x1}},
  1050  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1051  		{name: "PINSRD/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1052  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x0}},
  1053  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x1}},
  1054  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x0}},
  1055  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x1}},
  1056  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1057  		{name: "PINSRD/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1058  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x0}},
  1059  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x1}},
  1060  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x0}},
  1061  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x1}},
  1062  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1063  		{name: "PINSRD/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1064  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x0}},
  1065  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x1}},
  1066  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x0}},
  1067  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x1}},
  1068  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1069  		{name: "PINSRD/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1070  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x0}},
  1071  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x1}},
  1072  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x0}},
  1073  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x1}},
  1074  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1075  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x42, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1076  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x0}},
  1077  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x1}},
  1078  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x0}},
  1079  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x1}},
  1080  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1081  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1082  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x0}},
  1083  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x1}},
  1084  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x0}},
  1085  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x1}},
  1086  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1087  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1088  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x0}},
  1089  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x1}},
  1090  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x0}},
  1091  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x1}},
  1092  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1093  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1094  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x0}},
  1095  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x1}},
  1096  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x0}},
  1097  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x1}},
  1098  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1099  		{name: "PINSRD/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x46, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1100  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x0}},
  1101  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x1}},
  1102  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x0}},
  1103  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x1}},
  1104  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1105  		{name: "PINSRD/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1106  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x0}},
  1107  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x1}},
  1108  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x0}},
  1109  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x1}},
  1110  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1111  		{name: "PINSRD/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1112  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x0}},
  1113  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x1}},
  1114  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x0}},
  1115  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x1}},
  1116  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1117  		{name: "PINSRD/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRD, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x44, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1118  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x0}},
  1119  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x20, 0x1}},
  1120  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x0}},
  1121  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x20, 0x1, 0x1}},
  1122  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1123  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1124  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x0}},
  1125  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x0, 0x1}},
  1126  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x0}},
  1127  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x0, 0x1, 0x1}},
  1128  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1129  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1130  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x0}},
  1131  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x28, 0x1}},
  1132  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x0}},
  1133  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x28, 0x1, 0x1}},
  1134  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1135  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1136  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x0}},
  1137  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x30, 0x1}},
  1138  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x0}},
  1139  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x30, 0x1, 0x1}},
  1140  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1141  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1142  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x0}},
  1143  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x20, 0x1}},
  1144  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x0}},
  1145  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x20, 0x1, 0x1}},
  1146  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1147  		{name: "PINSRQ/src=AX/index=R12/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x20, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1148  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x0}},
  1149  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x0, 0x1}},
  1150  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x0}},
  1151  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x0, 0x1, 0x1}},
  1152  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1153  		{name: "PINSRQ/src=AX/index=AX/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1154  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x0}},
  1155  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x28, 0x1}},
  1156  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x0}},
  1157  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x28, 0x1, 0x1}},
  1158  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1159  		{name: "PINSRQ/src=AX/index=BP/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x28, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1160  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x0}},
  1161  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x30, 0x1}},
  1162  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x0}},
  1163  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x30, 0x1, 0x1}},
  1164  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1165  		{name: "PINSRQ/src=AX/index=SI/scale=1/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 1, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x30, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1166  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x0}},
  1167  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0x60, 0x1}},
  1168  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x0}},
  1169  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0x60, 0x1, 0x1}},
  1170  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1171  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1172  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x0}},
  1173  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x40, 0x1}},
  1174  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x0}},
  1175  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x40, 0x1, 0x1}},
  1176  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1177  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1178  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x0}},
  1179  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x68, 0x1}},
  1180  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x0}},
  1181  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x68, 0x1, 0x1}},
  1182  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1183  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1184  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x0}},
  1185  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x70, 0x1}},
  1186  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x0}},
  1187  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x70, 0x1, 0x1}},
  1188  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1189  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1190  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x0}},
  1191  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0x60, 0x1}},
  1192  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x0}},
  1193  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0x60, 0x1, 0x1}},
  1194  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1195  		{name: "PINSRQ/src=AX/index=R12/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0x60, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1196  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x0}},
  1197  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x40, 0x1}},
  1198  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x0}},
  1199  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x40, 0x1, 0x1}},
  1200  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1201  		{name: "PINSRQ/src=AX/index=AX/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x40, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1202  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x0}},
  1203  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x68, 0x1}},
  1204  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x0}},
  1205  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x68, 0x1, 0x1}},
  1206  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1207  		{name: "PINSRQ/src=AX/index=BP/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x68, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1208  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x0}},
  1209  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x70, 0x1}},
  1210  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x0}},
  1211  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x70, 0x1, 0x1}},
  1212  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1213  		{name: "PINSRQ/src=AX/index=SI/scale=2/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 2, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x70, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1214  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x0}},
  1215  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xa0, 0x1}},
  1216  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x0}},
  1217  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xa0, 0x1, 0x1}},
  1218  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1219  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1220  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x0}},
  1221  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0x80, 0x1}},
  1222  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x0}},
  1223  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0x80, 0x1, 0x1}},
  1224  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1225  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1226  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x0}},
  1227  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xa8, 0x1}},
  1228  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x0}},
  1229  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xa8, 0x1, 0x1}},
  1230  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1231  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1232  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x0}},
  1233  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xb0, 0x1}},
  1234  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x0}},
  1235  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xb0, 0x1, 0x1}},
  1236  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1237  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1238  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x0}},
  1239  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xa0, 0x1}},
  1240  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x0}},
  1241  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xa0, 0x1, 0x1}},
  1242  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1243  		{name: "PINSRQ/src=AX/index=R12/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xa0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1244  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x0}},
  1245  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0x80, 0x1}},
  1246  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x0}},
  1247  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0x80, 0x1, 0x1}},
  1248  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1249  		{name: "PINSRQ/src=AX/index=AX/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1250  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x0}},
  1251  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xa8, 0x1}},
  1252  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x0}},
  1253  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xa8, 0x1, 0x1}},
  1254  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1255  		{name: "PINSRQ/src=AX/index=BP/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xa8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1256  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x0}},
  1257  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xb0, 0x1}},
  1258  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x0}},
  1259  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xb0, 0x1, 0x1}},
  1260  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1261  		{name: "PINSRQ/src=AX/index=SI/scale=4/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 4, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xb0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1262  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x0}},
  1263  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x4, 0xe0, 0x1}},
  1264  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x0}},
  1265  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x44, 0xe0, 0x1, 0x1}},
  1266  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1267  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x4a, 0xf, 0x3a, 0x22, 0x84, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1268  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x0}},
  1269  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xc0, 0x1}},
  1270  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x0}},
  1271  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xc0, 0x1, 0x1}},
  1272  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1273  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1274  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x0}},
  1275  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xe8, 0x1}},
  1276  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x0}},
  1277  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xe8, 0x1, 0x1}},
  1278  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1279  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1280  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x0}},
  1281  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x4, 0xf0, 0x1}},
  1282  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x0}},
  1283  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x44, 0xf0, 0x1, 0x1}},
  1284  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 0}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1285  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X0/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX0, arg: 1}, exp: []byte{0x66, 0x48, 0xf, 0x3a, 0x22, 0x84, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1286  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x0}},
  1287  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x2c, 0xe0, 0x1}},
  1288  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x0}},
  1289  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0x6c, 0xe0, 0x1, 0x1}},
  1290  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1291  		{name: "PINSRQ/src=AX/index=R12/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegR12, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4e, 0xf, 0x3a, 0x22, 0xac, 0xe0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1292  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x0}},
  1293  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xc0, 0x1}},
  1294  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x0}},
  1295  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xc0, 0x1, 0x1}},
  1296  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1297  		{name: "PINSRQ/src=AX/index=AX/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegAX, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xc0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1298  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x0}},
  1299  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xe8, 0x1}},
  1300  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x0}},
  1301  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xe8, 0x1, 0x1}},
  1302  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1303  		{name: "PINSRQ/src=AX/index=BP/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegBP, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xe8, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1304  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x0}},
  1305  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=0/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 0, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x2c, 0xf0, 0x1}},
  1306  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x0}},
  1307  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=1/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 1, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0x6c, 0xf0, 0x1, 0x1}},
  1308  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=0", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 0}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x0}},
  1309  		{name: "PINSRQ/src=AX/index=SI/scale=8/offset=2147483647/dst=X13/arg=1", n: &nodeImpl{instruction: PINSRQ, srcReg: RegAX, srcMemIndex: RegSI, srcMemScale: 8, srcConst: 2147483647, dstReg: RegX13, arg: 1}, exp: []byte{0x66, 0x4c, 0xf, 0x3a, 0x22, 0xac, 0xf0, 0xff, 0xff, 0xff, 0x7f, 0x1}},
  1310  		{name: "ADDL/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x3, 0x8}},
  1311  		{name: "ADDL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x3, 0xc, 0xb0}},
  1312  		{name: "ADDL/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x3, 0x48, 0x1}},
  1313  		{name: "ADDL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x3, 0x4c, 0xb0, 0x1}},
  1314  		{name: "ADDL/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x3, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1315  		{name: "ADDL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x3, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1316  		{name: "ADDL/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x3, 0xa}},
  1317  		{name: "ADDL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x3, 0xc, 0xb2}},
  1318  		{name: "ADDL/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x3, 0x4a, 0x1}},
  1319  		{name: "ADDL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x3, 0x4c, 0xb2, 0x1}},
  1320  		{name: "ADDL/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x3, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1321  		{name: "ADDL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x3, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1322  		{name: "ADDQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x3, 0x8}},
  1323  		{name: "ADDQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x3, 0xc, 0xb0}},
  1324  		{name: "ADDQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x3, 0x48, 0x1}},
  1325  		{name: "ADDQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x3, 0x4c, 0xb0, 0x1}},
  1326  		{name: "ADDQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x3, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1327  		{name: "ADDQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x3, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1328  		{name: "ADDQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x3, 0xa}},
  1329  		{name: "ADDQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x3, 0xc, 0xb2}},
  1330  		{name: "ADDQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x3, 0x4a, 0x1}},
  1331  		{name: "ADDQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x3, 0x4c, 0xb2, 0x1}},
  1332  		{name: "ADDQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x3, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1333  		{name: "ADDQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: ADDQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x3, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1334  		{name: "CMPL/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x39, 0x8}},
  1335  		{name: "CMPL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x39, 0xc, 0xb0}},
  1336  		{name: "CMPL/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x39, 0x48, 0x1}},
  1337  		{name: "CMPL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x39, 0x4c, 0xb0, 0x1}},
  1338  		{name: "CMPL/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x39, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1339  		{name: "CMPL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x39, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1340  		{name: "CMPL/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x39, 0xa}},
  1341  		{name: "CMPL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x39, 0xc, 0xb2}},
  1342  		{name: "CMPL/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x39, 0x4a, 0x1}},
  1343  		{name: "CMPL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x39, 0x4c, 0xb2, 0x1}},
  1344  		{name: "CMPL/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x39, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1345  		{name: "CMPL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x39, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1346  		{name: "CMPQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x39, 0x8}},
  1347  		{name: "CMPQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x39, 0xc, 0xb0}},
  1348  		{name: "CMPQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x39, 0x48, 0x1}},
  1349  		{name: "CMPQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x39, 0x4c, 0xb0, 0x1}},
  1350  		{name: "CMPQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x39, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1351  		{name: "CMPQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x39, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1352  		{name: "CMPQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x39, 0xa}},
  1353  		{name: "CMPQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x39, 0xc, 0xb2}},
  1354  		{name: "CMPQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x39, 0x4a, 0x1}},
  1355  		{name: "CMPQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x39, 0x4c, 0xb2, 0x1}},
  1356  		{name: "CMPQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x39, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1357  		{name: "CMPQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: CMPQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x39, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1358  		{name: "LEAQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x8d, 0x8}},
  1359  		{name: "LEAQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8d, 0xc, 0xb0}},
  1360  		{name: "LEAQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x8d, 0x48, 0x1}},
  1361  		{name: "LEAQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8d, 0x4c, 0xb0, 0x1}},
  1362  		{name: "LEAQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x8d, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1363  		{name: "LEAQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8d, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1364  		{name: "LEAQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x8d, 0xa}},
  1365  		{name: "LEAQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8d, 0xc, 0xb2}},
  1366  		{name: "LEAQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x8d, 0x4a, 0x1}},
  1367  		{name: "LEAQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8d, 0x4c, 0xb2, 0x1}},
  1368  		{name: "LEAQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x8d, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1369  		{name: "LEAQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: LEAQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8d, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1370  		{name: "MOVBLSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xbe, 0x8}},
  1371  		{name: "MOVBLSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbe, 0xc, 0xb0}},
  1372  		{name: "MOVBLSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xbe, 0x48, 0x1}},
  1373  		{name: "MOVBLSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbe, 0x4c, 0xb0, 0x1}},
  1374  		{name: "MOVBLSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xbe, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1375  		{name: "MOVBLSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbe, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1376  		{name: "MOVBLSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbe, 0xa}},
  1377  		{name: "MOVBLSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbe, 0xc, 0xb2}},
  1378  		{name: "MOVBLSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbe, 0x4a, 0x1}},
  1379  		{name: "MOVBLSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbe, 0x4c, 0xb2, 0x1}},
  1380  		{name: "MOVBLSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbe, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1381  		{name: "MOVBLSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbe, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1382  		{name: "MOVBLZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xb6, 0x8}},
  1383  		{name: "MOVBLZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb6, 0xc, 0xb0}},
  1384  		{name: "MOVBLZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xb6, 0x48, 0x1}},
  1385  		{name: "MOVBLZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb6, 0x4c, 0xb0, 0x1}},
  1386  		{name: "MOVBLZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xb6, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1387  		{name: "MOVBLZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb6, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1388  		{name: "MOVBLZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb6, 0xa}},
  1389  		{name: "MOVBLZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb6, 0xc, 0xb2}},
  1390  		{name: "MOVBLZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb6, 0x4a, 0x1}},
  1391  		{name: "MOVBLZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb6, 0x4c, 0xb2, 0x1}},
  1392  		{name: "MOVBLZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb6, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1393  		{name: "MOVBLZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBLZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb6, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1394  		{name: "MOVBQSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbe, 0x8}},
  1395  		{name: "MOVBQSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbe, 0xc, 0xb0}},
  1396  		{name: "MOVBQSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbe, 0x48, 0x1}},
  1397  		{name: "MOVBQSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbe, 0x4c, 0xb0, 0x1}},
  1398  		{name: "MOVBQSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbe, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1399  		{name: "MOVBQSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbe, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1400  		{name: "MOVBQSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbe, 0xa}},
  1401  		{name: "MOVBQSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbe, 0xc, 0xb2}},
  1402  		{name: "MOVBQSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbe, 0x4a, 0x1}},
  1403  		{name: "MOVBQSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbe, 0x4c, 0xb2, 0x1}},
  1404  		{name: "MOVBQSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbe, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1405  		{name: "MOVBQSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbe, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1406  		{name: "MOVBQZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb6, 0x8}},
  1407  		{name: "MOVBQZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb6, 0xc, 0xb0}},
  1408  		{name: "MOVBQZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb6, 0x48, 0x1}},
  1409  		{name: "MOVBQZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb6, 0x4c, 0xb0, 0x1}},
  1410  		{name: "MOVBQZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb6, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1411  		{name: "MOVBQZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb6, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1412  		{name: "MOVBQZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb6, 0xa}},
  1413  		{name: "MOVBQZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb6, 0xc, 0xb2}},
  1414  		{name: "MOVBQZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb6, 0x4a, 0x1}},
  1415  		{name: "MOVBQZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb6, 0x4c, 0xb2, 0x1}},
  1416  		{name: "MOVBQZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb6, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1417  		{name: "MOVBQZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVBQZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb6, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1418  		{name: "MOVLQSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x63, 0x8}},
  1419  		{name: "MOVLQSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x63, 0xc, 0xb0}},
  1420  		{name: "MOVLQSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x63, 0x48, 0x1}},
  1421  		{name: "MOVLQSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x63, 0x4c, 0xb0, 0x1}},
  1422  		{name: "MOVLQSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x63, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1423  		{name: "MOVLQSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x63, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1424  		{name: "MOVLQSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x63, 0xa}},
  1425  		{name: "MOVLQSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x63, 0xc, 0xb2}},
  1426  		{name: "MOVLQSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x63, 0x4a, 0x1}},
  1427  		{name: "MOVLQSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x63, 0x4c, 0xb2, 0x1}},
  1428  		{name: "MOVLQSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x63, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1429  		{name: "MOVLQSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x63, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1430  		{name: "MOVLQZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x8b, 0x8}},
  1431  		{name: "MOVLQZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0xc, 0xb0}},
  1432  		{name: "MOVLQZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x8b, 0x48, 0x1}},
  1433  		{name: "MOVLQZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x4c, 0xb0, 0x1}},
  1434  		{name: "MOVLQZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x8b, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1435  		{name: "MOVLQZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1436  		{name: "MOVLQZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0xa}},
  1437  		{name: "MOVLQZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0xc, 0xb2}},
  1438  		{name: "MOVLQZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x4a, 0x1}},
  1439  		{name: "MOVLQZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x4c, 0xb2, 0x1}},
  1440  		{name: "MOVLQZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1441  		{name: "MOVLQZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVLQZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1442  		{name: "MOVL/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x8b, 0x8}},
  1443  		{name: "MOVL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0xc, 0xb0}},
  1444  		{name: "MOVL/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x8b, 0x48, 0x1}},
  1445  		{name: "MOVL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x4c, 0xb0, 0x1}},
  1446  		{name: "MOVL/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x8b, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1447  		{name: "MOVL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0x8b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1448  		{name: "MOVL/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x6e, 0x18}},
  1449  		{name: "MOVL/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x6e, 0x1c, 0xb0}},
  1450  		{name: "MOVL/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x6e, 0x58, 0x1}},
  1451  		{name: "MOVL/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x6e, 0x5c, 0xb0, 0x1}},
  1452  		{name: "MOVL/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x6e, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1453  		{name: "MOVL/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x6e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1454  		{name: "MOVL/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0xa}},
  1455  		{name: "MOVL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0xc, 0xb2}},
  1456  		{name: "MOVL/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x4a, 0x1}},
  1457  		{name: "MOVL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x4c, 0xb2, 0x1}},
  1458  		{name: "MOVL/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0x8b, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1459  		{name: "MOVL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0x8b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1460  		{name: "MOVL/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0x1a}},
  1461  		{name: "MOVL/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x6e, 0x1c, 0xb2}},
  1462  		{name: "MOVL/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0x5a, 0x1}},
  1463  		{name: "MOVL/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x6e, 0x5c, 0xb2, 0x1}},
  1464  		{name: "MOVL/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x6e, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1465  		{name: "MOVL/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVL, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x6e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1466  		{name: "MOVQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x8b, 0x8}},
  1467  		{name: "MOVQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8b, 0xc, 0xb0}},
  1468  		{name: "MOVQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x8b, 0x48, 0x1}},
  1469  		{name: "MOVQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8b, 0x4c, 0xb0, 0x1}},
  1470  		{name: "MOVQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x8b, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1471  		{name: "MOVQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x8b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1472  		{name: "MOVQ/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x7e, 0x18}},
  1473  		{name: "MOVQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x7e, 0x1c, 0xb0}},
  1474  		{name: "MOVQ/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x7e, 0x58, 0x1}},
  1475  		{name: "MOVQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x7e, 0x5c, 0xb0, 0x1}},
  1476  		{name: "MOVQ/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x7e, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1477  		{name: "MOVQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x7e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1478  		{name: "MOVQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x8b, 0xa}},
  1479  		{name: "MOVQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8b, 0xc, 0xb2}},
  1480  		{name: "MOVQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x8b, 0x4a, 0x1}},
  1481  		{name: "MOVQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8b, 0x4c, 0xb2, 0x1}},
  1482  		{name: "MOVQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x8b, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1483  		{name: "MOVQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x8b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1484  		{name: "MOVQ/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0x1a}},
  1485  		{name: "MOVQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x7e, 0x1c, 0xb2}},
  1486  		{name: "MOVQ/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0x5a, 0x1}},
  1487  		{name: "MOVQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x7e, 0x5c, 0xb2, 0x1}},
  1488  		{name: "MOVQ/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x7e, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1489  		{name: "MOVQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: MOVQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x7e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1490  		{name: "MOVWLSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xbf, 0x8}},
  1491  		{name: "MOVWLSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbf, 0xc, 0xb0}},
  1492  		{name: "MOVWLSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xbf, 0x48, 0x1}},
  1493  		{name: "MOVWLSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbf, 0x4c, 0xb0, 0x1}},
  1494  		{name: "MOVWLSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xbf, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1495  		{name: "MOVWLSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xbf, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1496  		{name: "MOVWLSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbf, 0xa}},
  1497  		{name: "MOVWLSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbf, 0xc, 0xb2}},
  1498  		{name: "MOVWLSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbf, 0x4a, 0x1}},
  1499  		{name: "MOVWLSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbf, 0x4c, 0xb2, 0x1}},
  1500  		{name: "MOVWLSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xbf, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1501  		{name: "MOVWLSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xbf, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1502  		{name: "MOVWLZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0xf, 0xb7, 0x8}},
  1503  		{name: "MOVWLZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb7, 0xc, 0xb0}},
  1504  		{name: "MOVWLZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0xf, 0xb7, 0x48, 0x1}},
  1505  		{name: "MOVWLZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb7, 0x4c, 0xb0, 0x1}},
  1506  		{name: "MOVWLZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0xf, 0xb7, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1507  		{name: "MOVWLZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x42, 0xf, 0xb7, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1508  		{name: "MOVWLZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb7, 0xa}},
  1509  		{name: "MOVWLZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb7, 0xc, 0xb2}},
  1510  		{name: "MOVWLZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb7, 0x4a, 0x1}},
  1511  		{name: "MOVWLZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb7, 0x4c, 0xb2, 0x1}},
  1512  		{name: "MOVWLZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x41, 0xf, 0xb7, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1513  		{name: "MOVWLZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWLZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x43, 0xf, 0xb7, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1514  		{name: "MOVWQSX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbf, 0x8}},
  1515  		{name: "MOVWQSX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbf, 0xc, 0xb0}},
  1516  		{name: "MOVWQSX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbf, 0x48, 0x1}},
  1517  		{name: "MOVWQSX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbf, 0x4c, 0xb0, 0x1}},
  1518  		{name: "MOVWQSX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xbf, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1519  		{name: "MOVWQSX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xbf, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1520  		{name: "MOVWQSX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbf, 0xa}},
  1521  		{name: "MOVWQSX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbf, 0xc, 0xb2}},
  1522  		{name: "MOVWQSX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbf, 0x4a, 0x1}},
  1523  		{name: "MOVWQSX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbf, 0x4c, 0xb2, 0x1}},
  1524  		{name: "MOVWQSX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xbf, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1525  		{name: "MOVWQSX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQSX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xbf, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1526  		{name: "MOVWQZX/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb7, 0x8}},
  1527  		{name: "MOVWQZX/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb7, 0xc, 0xb0}},
  1528  		{name: "MOVWQZX/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb7, 0x48, 0x1}},
  1529  		{name: "MOVWQZX/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb7, 0x4c, 0xb0, 0x1}},
  1530  		{name: "MOVWQZX/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0xf, 0xb7, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1531  		{name: "MOVWQZX/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0xf, 0xb7, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1532  		{name: "MOVWQZX/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb7, 0xa}},
  1533  		{name: "MOVWQZX/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb7, 0xc, 0xb2}},
  1534  		{name: "MOVWQZX/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb7, 0x4a, 0x1}},
  1535  		{name: "MOVWQZX/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb7, 0x4c, 0xb2, 0x1}},
  1536  		{name: "MOVWQZX/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0xf, 0xb7, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1537  		{name: "MOVWQZX/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: MOVWQZX, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0xf, 0xb7, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1538  		{name: "SUBQ/baseReg=AX/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x48, 0x2b, 0x8}},
  1539  		{name: "SUBQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x2b, 0xc, 0xb0}},
  1540  		{name: "SUBQ/baseReg=AX/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x48, 0x2b, 0x48, 0x1}},
  1541  		{name: "SUBQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x2b, 0x4c, 0xb0, 0x1}},
  1542  		{name: "SUBQ/baseReg=AX/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x48, 0x2b, 0x88, 0xff, 0xff, 0xff, 0x7f}},
  1543  		{name: "SUBQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4a, 0x2b, 0x8c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1544  		{name: "SUBQ/baseReg=R10/offset=0x0/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegCX}, exp: []byte{0x49, 0x2b, 0xa}},
  1545  		{name: "SUBQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x2b, 0xc, 0xb2}},
  1546  		{name: "SUBQ/baseReg=R10/offset=0x1/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegCX}, exp: []byte{0x49, 0x2b, 0x4a, 0x1}},
  1547  		{name: "SUBQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x2b, 0x4c, 0xb2, 0x1}},
  1548  		{name: "SUBQ/baseReg=R10/offset=0x7fffffff/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegCX}, exp: []byte{0x49, 0x2b, 0x8a, 0xff, 0xff, 0xff, 0x7f}},
  1549  		{name: "SUBQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=CX", n: &nodeImpl{instruction: SUBQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegCX}, exp: []byte{0x4b, 0x2b, 0x8c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1550  		{name: "SUBSD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf2, 0xf, 0x5c, 0x18}},
  1551  		{name: "SUBSD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x42, 0xf, 0x5c, 0x1c, 0xb0}},
  1552  		{name: "SUBSD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf2, 0xf, 0x5c, 0x58, 0x1}},
  1553  		{name: "SUBSD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x42, 0xf, 0x5c, 0x5c, 0xb0, 0x1}},
  1554  		{name: "SUBSD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf2, 0xf, 0x5c, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1555  		{name: "SUBSD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x42, 0xf, 0x5c, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1556  		{name: "SUBSD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0x1a}},
  1557  		{name: "SUBSD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x43, 0xf, 0x5c, 0x1c, 0xb2}},
  1558  		{name: "SUBSD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0x5a, 0x1}},
  1559  		{name: "SUBSD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x43, 0xf, 0x5c, 0x5c, 0xb2, 0x1}},
  1560  		{name: "SUBSD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf2, 0x41, 0xf, 0x5c, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1561  		{name: "SUBSD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf2, 0x43, 0xf, 0x5c, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1562  		{name: "SUBSS/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x5c, 0x18}},
  1563  		{name: "SUBSS/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x5c, 0x1c, 0xb0}},
  1564  		{name: "SUBSS/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x5c, 0x58, 0x1}},
  1565  		{name: "SUBSS/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x5c, 0x5c, 0xb0, 0x1}},
  1566  		{name: "SUBSS/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0xf, 0x5c, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1567  		{name: "SUBSS/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x42, 0xf, 0x5c, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1568  		{name: "SUBSS/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0x1a}},
  1569  		{name: "SUBSS/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x5c, 0x1c, 0xb2}},
  1570  		{name: "SUBSS/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0x5a, 0x1}},
  1571  		{name: "SUBSS/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x5c, 0x5c, 0xb2, 0x1}},
  1572  		{name: "SUBSS/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf3, 0x41, 0xf, 0x5c, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1573  		{name: "SUBSS/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: SUBSS, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0xf3, 0x43, 0xf, 0x5c, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1574  		{name: "UCOMISD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x2e, 0x18}},
  1575  		{name: "UCOMISD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x2e, 0x1c, 0xb0}},
  1576  		{name: "UCOMISD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x2e, 0x58, 0x1}},
  1577  		{name: "UCOMISD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x2e, 0x5c, 0xb0, 0x1}},
  1578  		{name: "UCOMISD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x2e, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1579  		{name: "UCOMISD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x2e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1580  		{name: "UCOMISD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0x1a}},
  1581  		{name: "UCOMISD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x2e, 0x1c, 0xb2}},
  1582  		{name: "UCOMISD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0x5a, 0x1}},
  1583  		{name: "UCOMISD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x2e, 0x5c, 0xb2, 0x1}},
  1584  		{name: "UCOMISD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x2e, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1585  		{name: "UCOMISD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x2e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1586  		{name: "UCOMISS/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0xf, 0x2e, 0x18}},
  1587  		{name: "UCOMISS/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x42, 0xf, 0x2e, 0x1c, 0xb0}},
  1588  		{name: "UCOMISS/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0xf, 0x2e, 0x58, 0x1}},
  1589  		{name: "UCOMISS/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x42, 0xf, 0x2e, 0x5c, 0xb0, 0x1}},
  1590  		{name: "UCOMISS/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0xf, 0x2e, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1591  		{name: "UCOMISS/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x42, 0xf, 0x2e, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1592  		{name: "UCOMISS/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x41, 0xf, 0x2e, 0x1a}},
  1593  		{name: "UCOMISS/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x43, 0xf, 0x2e, 0x1c, 0xb2}},
  1594  		{name: "UCOMISS/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x41, 0xf, 0x2e, 0x5a, 0x1}},
  1595  		{name: "UCOMISS/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x43, 0xf, 0x2e, 0x5c, 0xb2, 0x1}},
  1596  		{name: "UCOMISS/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x41, 0xf, 0x2e, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1597  		{name: "UCOMISS/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: UCOMISS, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x43, 0xf, 0x2e, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1598  		{name: "PMOVSXBW/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x20, 0x18}},
  1599  		{name: "PMOVSXBW/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x20, 0x1c, 0xb0}},
  1600  		{name: "PMOVSXBW/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x20, 0x58, 0x1}},
  1601  		{name: "PMOVSXBW/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x20, 0x5c, 0xb0, 0x1}},
  1602  		{name: "PMOVSXBW/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x20, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1603  		{name: "PMOVSXBW/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x20, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1604  		{name: "PMOVSXBW/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0x1a}},
  1605  		{name: "PMOVSXBW/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x20, 0x1c, 0xb2}},
  1606  		{name: "PMOVSXBW/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0x5a, 0x1}},
  1607  		{name: "PMOVSXBW/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x20, 0x5c, 0xb2, 0x1}},
  1608  		{name: "PMOVSXBW/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x20, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1609  		{name: "PMOVSXBW/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXBW, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x20, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1610  		{name: "PMOVSXWD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x23, 0x18}},
  1611  		{name: "PMOVSXWD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x23, 0x1c, 0xb0}},
  1612  		{name: "PMOVSXWD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x23, 0x58, 0x1}},
  1613  		{name: "PMOVSXWD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x23, 0x5c, 0xb0, 0x1}},
  1614  		{name: "PMOVSXWD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x23, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1615  		{name: "PMOVSXWD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x23, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1616  		{name: "PMOVSXWD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0x1a}},
  1617  		{name: "PMOVSXWD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x23, 0x1c, 0xb2}},
  1618  		{name: "PMOVSXWD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0x5a, 0x1}},
  1619  		{name: "PMOVSXWD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x23, 0x5c, 0xb2, 0x1}},
  1620  		{name: "PMOVSXWD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x23, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1621  		{name: "PMOVSXWD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXWD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x23, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1622  		{name: "PMOVSXDQ/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x25, 0x18}},
  1623  		{name: "PMOVSXDQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x25, 0x1c, 0xb0}},
  1624  		{name: "PMOVSXDQ/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x25, 0x58, 0x1}},
  1625  		{name: "PMOVSXDQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x25, 0x5c, 0xb0, 0x1}},
  1626  		{name: "PMOVSXDQ/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x25, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1627  		{name: "PMOVSXDQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x25, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1628  		{name: "PMOVSXDQ/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0x1a}},
  1629  		{name: "PMOVSXDQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x25, 0x1c, 0xb2}},
  1630  		{name: "PMOVSXDQ/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0x5a, 0x1}},
  1631  		{name: "PMOVSXDQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x25, 0x5c, 0xb2, 0x1}},
  1632  		{name: "PMOVSXDQ/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x25, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1633  		{name: "PMOVSXDQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVSXDQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x25, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1634  		{name: "PMOVZXBW/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x30, 0x18}},
  1635  		{name: "PMOVZXBW/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x30, 0x1c, 0xb0}},
  1636  		{name: "PMOVZXBW/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x30, 0x58, 0x1}},
  1637  		{name: "PMOVZXBW/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x30, 0x5c, 0xb0, 0x1}},
  1638  		{name: "PMOVZXBW/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x30, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1639  		{name: "PMOVZXBW/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x30, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1640  		{name: "PMOVZXBW/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0x1a}},
  1641  		{name: "PMOVZXBW/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x30, 0x1c, 0xb2}},
  1642  		{name: "PMOVZXBW/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0x5a, 0x1}},
  1643  		{name: "PMOVZXBW/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x30, 0x5c, 0xb2, 0x1}},
  1644  		{name: "PMOVZXBW/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x30, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1645  		{name: "PMOVZXBW/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXBW, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x30, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1646  		{name: "PMOVZXWD/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x33, 0x18}},
  1647  		{name: "PMOVZXWD/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x33, 0x1c, 0xb0}},
  1648  		{name: "PMOVZXWD/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x33, 0x58, 0x1}},
  1649  		{name: "PMOVZXWD/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x33, 0x5c, 0xb0, 0x1}},
  1650  		{name: "PMOVZXWD/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x33, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1651  		{name: "PMOVZXWD/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x33, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1652  		{name: "PMOVZXWD/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0x1a}},
  1653  		{name: "PMOVZXWD/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x33, 0x1c, 0xb2}},
  1654  		{name: "PMOVZXWD/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0x5a, 0x1}},
  1655  		{name: "PMOVZXWD/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x33, 0x5c, 0xb2, 0x1}},
  1656  		{name: "PMOVZXWD/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x33, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1657  		{name: "PMOVZXWD/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXWD, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x33, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1658  		{name: "PMOVZXDQ/baseReg=AX/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x35, 0x18}},
  1659  		{name: "PMOVZXDQ/baseReg=AX/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x35, 0x1c, 0xb0}},
  1660  		{name: "PMOVZXDQ/baseReg=AX/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x35, 0x58, 0x1}},
  1661  		{name: "PMOVZXDQ/baseReg=AX/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x35, 0x5c, 0xb0, 0x1}},
  1662  		{name: "PMOVZXDQ/baseReg=AX/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0xf, 0x38, 0x35, 0x98, 0xff, 0xff, 0xff, 0x7f}},
  1663  		{name: "PMOVZXDQ/baseReg=AX/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegAX, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x42, 0xf, 0x38, 0x35, 0x9c, 0xb0, 0xff, 0xff, 0xff, 0x7f}},
  1664  		{name: "PMOVZXDQ/baseReg=R10/offset=0x0/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x0, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0x1a}},
  1665  		{name: "PMOVZXDQ/baseReg=R10/offset=0x0/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x0, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x35, 0x1c, 0xb2}},
  1666  		{name: "PMOVZXDQ/baseReg=R10/offset=0x1/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x1, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0x5a, 0x1}},
  1667  		{name: "PMOVZXDQ/baseReg=R10/offset=0x1/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x1, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x35, 0x5c, 0xb2, 0x1}},
  1668  		{name: "PMOVZXDQ/baseReg=R10/offset=0x7fffffff/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x7fffffff, dstReg: RegX3}, exp: []byte{0x66, 0x41, 0xf, 0x38, 0x35, 0x9a, 0xff, 0xff, 0xff, 0x7f}},
  1669  		{name: "PMOVZXDQ/baseReg=R10/offset=0x7fffffff/index=R14/scale=4/dstReg=X3", n: &nodeImpl{instruction: PMOVZXDQ, srcReg: RegR10, srcConst: 0x7fffffff, srcMemIndex: RegR14, srcMemScale: 4, dstReg: RegX3}, exp: []byte{0x66, 0x43, 0xf, 0x38, 0x35, 0x9c, 0xb2, 0xff, 0xff, 0xff, 0x7f}},
  1670  	}
  1671  
  1672  	for _, tc := range tests {
  1673  		code := asm.CodeSegment{}
  1674  		defer func() { require.NoError(t, code.Unmap()) }()
  1675  
  1676  		tc.n.types = operandTypesMemoryToRegister
  1677  		a := NewAssembler()
  1678  		buf := code.NextCodeSection()
  1679  		err := a.encodeMemoryToRegister(buf, tc.n)
  1680  		require.NoError(t, err, tc.name)
  1681  
  1682  		err = a.Assemble(buf)
  1683  		require.NoError(t, err, tc.name)
  1684  
  1685  		actual := buf.Bytes()
  1686  		require.Equal(t, tc.exp, actual, tc.name)
  1687  	}
  1688  }
  1689  
  1690  func TestAssemblerImpl_EncodeConstToRegister(t *testing.T) {
  1691  	tests := []struct {
  1692  		name string
  1693  		n    *nodeImpl
  1694  		exp  []byte
  1695  	}{
  1696  		{
  1697  			name: "psraw xmm10, 1",
  1698  			n:    &nodeImpl{instruction: PSRAW, types: operandTypesRegisterToRegister, srcConst: 1, dstReg: RegX10},
  1699  			exp:  []byte{0x66, 0x41, 0xf, 0x71, 0xe2, 0x1},
  1700  		},
  1701  		{
  1702  			name: "psraw xmm10, 8",
  1703  			n:    &nodeImpl{instruction: PSRAW, types: operandTypesRegisterToRegister, srcConst: 8, dstReg: RegX10},
  1704  			exp:  []byte{0x66, 0x41, 0xf, 0x71, 0xe2, 0x8},
  1705  		},
  1706  		{
  1707  			name: "psrlw xmm10, 1",
  1708  			n:    &nodeImpl{instruction: PSRLW, types: operandTypesRegisterToRegister, srcConst: 1, dstReg: RegX10},
  1709  			exp:  []byte{0x66, 0x41, 0xf, 0x71, 0xd2, 0x1},
  1710  		},
  1711  		{
  1712  			name: "psrlw xmm10, 8",
  1713  			n:    &nodeImpl{instruction: PSRLW, types: operandTypesRegisterToRegister, srcConst: 8, dstReg: RegX10},
  1714  			exp:  []byte{0x66, 0x41, 0xf, 0x71, 0xd2, 0x8},
  1715  		},
  1716  		{
  1717  			name: "psllw xmm10, 1",
  1718  			n:    &nodeImpl{instruction: PSLLW, types: operandTypesRegisterToRegister, srcConst: 1, dstReg: RegX10},
  1719  			exp:  []byte{0x66, 0x41, 0xf, 0x71, 0xf2, 0x1},
  1720  		},
  1721  		{
  1722  			name: "psllw xmm10, 8",
  1723  			n:    &nodeImpl{instruction: PSLLW, types: operandTypesRegisterToRegister, srcConst: 8, dstReg: RegX10},
  1724  			exp:  []byte{0x66, 0x41, 0xf, 0x71, 0xf2, 0x8},
  1725  		},
  1726  		{
  1727  			name: "psrad xmm10, 0x1f",
  1728  			n:    &nodeImpl{instruction: PSRAD, types: operandTypesRegisterToRegister, srcConst: 0x1f, dstReg: RegX10},
  1729  			exp:  []byte{0x66, 0x41, 0xf, 0x72, 0xe2, 0x1f},
  1730  		},
  1731  	}
  1732  
  1733  	for _, tt := range tests {
  1734  		code := asm.CodeSegment{}
  1735  		defer func() { require.NoError(t, code.Unmap()) }()
  1736  
  1737  		tc := tt
  1738  		a := NewAssembler()
  1739  		buf := code.NextCodeSection()
  1740  		err := a.encodeConstToRegister(buf, tc.n)
  1741  		require.NoError(t, err, tc.name)
  1742  
  1743  		err = a.Assemble(buf)
  1744  		require.NoError(t, err, tc.name)
  1745  
  1746  		actual := buf.Bytes()
  1747  		require.Equal(t, tc.exp, actual, tc.name)
  1748  	}
  1749  }
  1750  

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