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17 package procfs
18
19 import "testing"
20
21 const (
22 cpuinfoArm7Legacy = `
23 Processor : ARMv7 Processor rev 5 (v7l)
24 processor : 0
25 BogoMIPS : 2400.00
26
27 processor : 1
28 BogoMIPS : 2400.00
29
30 Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt
31 CPU implementer : 0x41
32 CPU architecture: 7
33 CPU variant : 0x0
34 CPU part : 0xc07
35 CPU revision : 5
36
37 Hardware : sun8i
38 Revision : 0000
39 Serial : 5400503583203c3c040e`
40
41 cpuinfoArm7LegacyV1 = `
42 Processor : ARMv6-compatible processor rev 5 (v6l)
43 BogoMIPS : 791.34
44 Features : swp half thumb fastmult vfp edsp java
45 CPU implementer : 0x41
46 CPU architecture: 6TEJ
47 CPU variant : 0x1
48 CPU part : 0xb36
49 CPU revision : 5
50
51 Hardware : IMAPX200
52 Revision : 0000
53 Serial : 0000000000000000`
54
55 cpuinfoArm7 = `
56 processor : 0
57 model name : ARMv7 Processor rev 3 (v7l)
58 BogoMIPS : 108.00
59 Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm crc32
60 CPU implementer : 0x41
61 CPU architecture: 7
62 CPU variant : 0x0
63 CPU part : 0xd08
64 CPU revision : 3
65
66 processor : 1
67 model name : ARMv7 Processor rev 3 (v7l)
68 BogoMIPS : 108.00
69 Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm crc32
70 CPU implementer : 0x41
71 CPU architecture: 7
72 CPU variant : 0x0
73 CPU part : 0xd08
74 CPU revision : 3
75
76 processor : 2
77 model name : ARMv7 Processor rev 3 (v7l)
78 BogoMIPS : 108.00
79 Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm crc32
80 CPU implementer : 0x41
81 CPU architecture: 7
82 CPU variant : 0x0
83 CPU part : 0xd08
84 CPU revision : 3
85
86 processor : 3
87 model name : ARMv7 Processor rev 3 (v7l)
88 BogoMIPS : 108.00
89 Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm crc32
90 CPU implementer : 0x41
91 CPU architecture: 7
92 CPU variant : 0x0
93 CPU part : 0xd08
94 CPU revision : 3
95
96 Hardware : BCM2835
97 Revision : c03111
98 `
99
100 cpuinfoS390x = `
101 vendor_id : IBM/S390
102 # processors : 4
103 bogomips per cpu: 3033.00
104 max thread id : 0
105 features : esan3 zarch stfle msa ldisp eimm dfp edat etf3eh highgprs te vx sie
106 facilities : 0 1 2 3 4 6 7 8 9 10 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 32 33 34 35 36 37 40 41 42 43 44 45 46 47 48 49 50 51 52 53 55 57 73 74 75 76 77 80 81 82 128 129 131
107 cache0 : level=1 type=Data scope=Private size=128K line_size=256 associativity=8
108 cache1 : level=1 type=Instruction scope=Private size=96K line_size=256 associativity=6
109 cache2 : level=2 type=Data scope=Private size=2048K line_size=256 associativity=8
110 cache3 : level=2 type=Instruction scope=Private size=2048K line_size=256 associativity=8
111 cache4 : level=3 type=Unified scope=Shared size=65536K line_size=256 associativity=16
112 cache5 : level=4 type=Unified scope=Shared size=491520K line_size=256 associativity=30
113 processor 0: version = FF, identification = 2733E8, machine = 2964
114 processor 1: version = FF, identification = 2733E8, machine = 2964
115 processor 2: version = FF, identification = 2733E8, machine = 2964
116 processor 3: version = FF, identification = 2733E8, machine = 2964
117
118 cpu number : 0
119 physical id : 2
120 core id : 0
121 siblings : 8
122 cpu cores : 4
123 cpu MHz dynamic : 5000
124 cpu MHz static : 5000
125
126 cpu number : 1
127 physical id : 2
128 core id : 0
129 siblings : 8
130 cpu cores : 4
131 cpu MHz dynamic : 5000
132 cpu MHz static : 5000
133
134 cpu number : 2
135 physical id : 2
136 core id : 1
137 siblings : 8
138 cpu cores : 4
139 cpu MHz dynamic : 5000
140 cpu MHz static : 5000
141
142 cpu number : 3
143 physical id : 2
144 core id : 1
145 siblings : 8
146 cpu cores : 4
147 cpu MHz dynamic : 5000
148 cpu MHz static : 5000
149 `
150
151 cpuinfoMips = `
152 system type : UBNT_E100
153 machine : Unknown
154 processor : 0
155 cpu model : Cavium Octeon+ V0.1
156 BogoMIPS : 1000.00
157 wait instruction : yes
158 microsecond timers : yes
159 tlb_entries : 64
160 extra interrupt vector : yes
161 hardware watchpoint : yes, count: 2, address/irw mask: [0x0ffc, 0x0ffb]
162 isa : mips1 mips2 mips3 mips4 mips5 mips64r2
163 ASEs implemented :
164 shadow register sets : 1
165 kscratch registers : 0
166 core : 0
167 VCED exceptions : not available
168 VCEI exceptions : not available
169
170 processor : 1
171 cpu model : Cavium Octeon+ V0.1
172 BogoMIPS : 1000.00
173 wait instruction : yes
174 microsecond timers : yes
175 tlb_entries : 64
176 extra interrupt vector : yes
177 hardware watchpoint : yes, count: 2, address/irw mask: [0x0ffc, 0x0ffb]
178 isa : mips1 mips2 mips3 mips4 mips5 mips64r2
179 ASEs implemented :
180 shadow register sets : 1
181 kscratch registers : 0
182 core : 1
183 VCED exceptions : not available
184 VCEI exceptions : not available
185
186 `
187
188 cpuinfoPpc64 = `
189 processor : 0
190 cpu : POWER7 (architected), altivec supported
191 clock : 3000.000000MHz
192 revision : 2.1 (pvr 003f 0201)
193
194 processor : 1
195 cpu : POWER7 (architected), altivec supported
196 clock : 3000.000000MHz
197 revision : 2.1 (pvr 003f 0201)
198
199 processor : 2
200 cpu : POWER7 (architected), altivec supported
201 clock : 3000.000000MHz
202 revision : 2.1 (pvr 003f 0201)
203
204 processor : 3
205 cpu : POWER7 (architected), altivec supported
206 clock : 3000.000000MHz
207 revision : 2.1 (pvr 003f 0201)
208
209 processor : 4
210 cpu : POWER7 (architected), altivec supported
211 clock : 3000.000000MHz
212 revision : 2.1 (pvr 003f 0201)
213
214 processor : 5
215 cpu : POWER7 (architected), altivec supported
216 clock : 3000.000000MHz
217 revision : 2.1 (pvr 003f 0201)
218
219 timebase : 512000000
220 platform : pSeries
221 model : IBM,8233-E8B
222 machine : CHRP IBM,8233-E8B
223 `
224
225 cpuinfoRiscv64 = `
226 processor : 0
227 hart : 0
228 isa : rv64imafdcsu
229 mmu : sv48
230
231 processor : 1
232 hart : 1
233 isa : rv64imafdcsu
234 mmu : sv48
235 `
236
237 cpuinfoLoong64 = `
238 system type : generic-loongson-machine
239
240 processor : 0
241 package : 0
242 core : 0
243 CPU Family : Loongson-64bit
244 Model Name : Loongson-3A5000
245 CPU Revision : 0x10
246 FPU Revision : 0x00
247 CPU MHz : 2500.00
248 BogoMIPS : 5000.00
249 TLB Entries : 2112
250 Address Sizes : 48 bits physical, 48 bits virtual
251 ISA : loongarch32 loongarch64
252 Features : cpucfg lam ual fpu complex crypto lvz
253 Hardware Watchpoint : yes, iwatch count: 0, dwatch count: 0
254
255 processor : 1
256 package : 0
257 core : 1
258 CPU Family : Loongson-64bit
259 Model Name : Loongson-3A5000
260 CPU Revision : 0x10
261 FPU Revision : 0x00
262 CPU MHz : 2500.00
263 BogoMIPS : 5000.00
264 TLB Entries : 2112
265 Address Sizes : 48 bits physical, 48 bits virtual
266 ISA : loongarch32 loongarch64
267 Features : cpucfg lam ual fpu complex crypto lvz
268 Hardware Watchpoint : yes, iwatch count: 0, dwatch count: 0
269
270 processor : 2
271 package : 0
272 core : 2
273 CPU Family : Loongson-64bit
274 Model Name : Loongson-3A5000
275 CPU Revision : 0x10
276 FPU Revision : 0x00
277 CPU MHz : 2500.00
278 BogoMIPS : 5000.00
279 TLB Entries : 2112
280 Address Sizes : 48 bits physical, 48 bits virtual
281 ISA : loongarch32 loongarch64
282 Features : cpucfg lam ual fpu complex crypto lvz
283 Hardware Watchpoint : yes, iwatch count: 0, dwatch count: 0
284
285 processor : 3
286 package : 0
287 core : 3
288 CPU Family : Loongson-64bit
289 Model Name : Loongson-3A5000
290 CPU Revision : 0x10
291 FPU Revision : 0x00
292 CPU MHz : 2500.00
293 BogoMIPS : 5000.00
294 TLB Entries : 2112
295 Address Sizes : 48 bits physical, 48 bits virtual
296 ISA : loongarch32 loongarch64
297 Features : cpucfg lam ual fpu complex crypto lvz
298 Hardware Watchpoint : yes, iwatch count: 0, dwatch count: 0
299 `
300 )
301
302 func TestCPUInfoX86(t *testing.T) {
303 parseCPUInfo = parseCPUInfoX86
304 cpuinfo, err := getProcFixtures(t).CPUInfo()
305 if err != nil {
306 t.Fatal(err)
307 }
308
309 if cpuinfo == nil {
310 t.Fatal("cpuinfo is nil")
311 }
312
313 if want, have := 8, len(cpuinfo); want != have {
314 t.Errorf("want number of processors %v, have %v", want, have)
315 }
316
317 if want, have := uint(7), cpuinfo[7].Processor; want != have {
318 t.Errorf("want processor %v, have %v", want, have)
319 }
320 if want, have := "GenuineIntel", cpuinfo[0].VendorID; want != have {
321 t.Errorf("want vendor %v, have %v", want, have)
322 }
323 if want, have := "6", cpuinfo[1].CPUFamily; want != have {
324 t.Errorf("want family %v, have %v", want, have)
325 }
326 if want, have := "142", cpuinfo[2].Model; want != have {
327 t.Errorf("want model %v, have %v", want, have)
328 }
329 if want, have := "Intel(R) Core(TM) i7-8650U CPU @ 1.90GHz", cpuinfo[3].ModelName; want != have {
330 t.Errorf("want model %v, have %v", want, have)
331 }
332 if want, have := uint(8), cpuinfo[4].Siblings; want != have {
333 t.Errorf("want siblings %v, have %v", want, have)
334 }
335 if want, have := "1", cpuinfo[5].CoreID; want != have {
336 t.Errorf("want core id %v, have %v", want, have)
337 }
338 if want, have := uint(4), cpuinfo[6].CPUCores; want != have {
339 t.Errorf("want cpu cores %v, have %v", want, have)
340 }
341 if want, have := "vme", cpuinfo[7].Flags[1]; want != have {
342 t.Errorf("want flag %v, have %v", want, have)
343 }
344 }
345
346 func TestCPUInfoParseARMLegacy(t *testing.T) {
347 cpuinfo, err := parseCPUInfoARM([]byte(cpuinfoArm7Legacy))
348 if err != nil || cpuinfo == nil {
349 t.Fatalf("unable to parse arm cpu info: %v", err)
350 }
351 if want, have := 2, len(cpuinfo); want != have {
352 t.Errorf("want number of processors %v, have %v", want, have)
353 }
354 if want, have := "ARMv7 Processor rev 5 (v7l)", cpuinfo[0].ModelName; want != have {
355 t.Errorf("want vendor %v, have %v", want, have)
356 }
357 if want, have := "thumb", cpuinfo[1].Flags[2]; want != have {
358 t.Errorf("want flag %v, have %v", want, have)
359 }
360 }
361
362 func TestCPUInfoParseARMLegacyV1(t *testing.T) {
363 cpuinfo, err := parseCPUInfoARM([]byte(cpuinfoArm7LegacyV1))
364 if err != nil || cpuinfo == nil {
365 t.Fatalf("unable to parse arm cpu info: %v", err)
366 }
367 if want, have := 1, len(cpuinfo); want != have {
368 t.Errorf("want number of processors %v, have %v", want, have)
369 }
370 if want, have := "ARMv6-compatible processor rev 5 (v6l)", cpuinfo[0].ModelName; want != have {
371 t.Errorf("want vendor %v, have %v", want, have)
372 }
373 if want, have := "thumb", cpuinfo[0].Flags[2]; want != have {
374 t.Errorf("want flag %v, have %v", want, have)
375 }
376 }
377
378 func TestCPUInfoParseARM(t *testing.T) {
379 cpuinfo, err := parseCPUInfoARM([]byte(cpuinfoArm7))
380 if err != nil || cpuinfo == nil {
381 t.Fatalf("unable to parse arm cpu info: %v", err)
382 }
383 if want, have := 4, len(cpuinfo); want != have {
384 t.Errorf("want number of processors %v, have %v", want, have)
385 }
386 if want, have := "ARMv7 Processor rev 3 (v7l)", cpuinfo[0].ModelName; want != have {
387 t.Errorf("want vendor %v, have %v", want, have)
388 }
389 if want, have := "thumb", cpuinfo[1].Flags[1]; want != have {
390 t.Errorf("want flag %v, have %v", want, have)
391 }
392 }
393
394 func TestCPUInfoParseS390X(t *testing.T) {
395 cpuinfo, err := parseCPUInfoS390X([]byte(cpuinfoS390x))
396 if err != nil || cpuinfo == nil {
397 t.Fatalf("unable to parse s390x cpu info: %v", err)
398 }
399 if want, have := 4, len(cpuinfo); want != have {
400 t.Errorf("want number of processors %v, have %v", want, have)
401 }
402 if want, have := "IBM/S390", cpuinfo[0].VendorID; want != have {
403 t.Errorf("want vendor %v, have %v", want, have)
404 }
405 if want, have := "ldisp", cpuinfo[1].Flags[4]; want != have {
406 t.Errorf("want flag %v, have %v", want, have)
407 }
408 if want, have := 5000.0, cpuinfo[2].CPUMHz; want != have {
409 t.Errorf("want cpu MHz %v, have %v", want, have)
410 }
411 if want, have := uint(8), cpuinfo[3].Siblings; want != have {
412 t.Errorf("want siblings %v, have %v", want, have)
413 }
414 if want, have := "1", cpuinfo[3].CoreID; want != have {
415 t.Errorf("want core id %v, have %v", want, have)
416 }
417 if want, have := uint(4), cpuinfo[2].CPUCores; want != have {
418 t.Errorf("want cpu cores %v, have %v", want, have)
419 }
420 if want, have := "2", cpuinfo[2].PhysicalID; want != have {
421 t.Errorf("want physical id %v, have %v", want, have)
422 }
423 }
424
425 func TestCPUInfoParseMips(t *testing.T) {
426 cpuinfo, err := parseCPUInfoMips([]byte(cpuinfoMips))
427 if err != nil || cpuinfo == nil {
428 t.Fatalf("unable to parse mips cpu info: %v", err)
429 }
430 if want, have := 2, len(cpuinfo); want != have {
431 t.Errorf("want number of processors %v, have %v", want, have)
432 }
433 if want, have := 1000.00, cpuinfo[0].BogoMips; want != have {
434 t.Errorf("want BogoMIPS %v, have %v", want, have)
435 }
436 if want, have := "Cavium Octeon+ V0.1", cpuinfo[1].ModelName; want != have {
437 t.Errorf("want ModelName '%v', have '%v'", want, have)
438 }
439 }
440
441 func TestCPUInfoParsePPC(t *testing.T) {
442 cpuinfo, err := parseCPUInfoPPC([]byte(cpuinfoPpc64))
443 if err != nil || cpuinfo == nil {
444 t.Fatalf("unable to parse ppc cpu info: %v", err)
445 }
446 if want, have := 6, len(cpuinfo); want != have {
447 t.Errorf("want number of processors %v, have %v", want, have)
448 }
449 if want, have := 3000.00, cpuinfo[2].CPUMHz; want != have {
450 t.Errorf("want cpu mhz %v, have %v", want, have)
451 }
452 }
453
454 func TestCPUInfoParseRISCV64(t *testing.T) {
455 cpuinfo, err := parseCPUInfoRISCV([]byte(cpuinfoRiscv64))
456 if err != nil || cpuinfo == nil {
457 t.Fatalf("unable to parse ppc cpu info: %v", err)
458 }
459 if want, have := 2, len(cpuinfo); want != have {
460 t.Errorf("want number of processors %v, have %v", want, have)
461 }
462 if want, have := "1", cpuinfo[1].CoreID; want != have {
463 t.Errorf("want CoreId %v, have %v", want, have)
464 }
465 if want, have := "rv64imafdcsu", cpuinfo[1].ModelName; want != have {
466 t.Errorf("want ModelName %v, have %v", want, have)
467 }
468 }
469
470 func TestCPUInfoParseLoong64(t *testing.T) {
471 cpuinfo, err := parseCPUInfoLoong([]byte(cpuinfoLoong64))
472 if err != nil || cpuinfo == nil {
473 t.Fatalf("unable to parse loong cpu info: %v", err)
474 }
475 if want, have := 4, len(cpuinfo); want != have {
476 t.Errorf("want number of processors %v, have %v", want, have)
477 }
478 if want, have := "Loongson-64bit", cpuinfo[1].CPUFamily; want != have {
479 t.Errorf("want CPUFamily '%v', have '%v'", want, have)
480 }
481 }
482
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